2006-08-26 16:55:02 -06:00
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#define NV03_BOOT_0 0x00100000
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# define NV03_BOOT_0_RAM_AMOUNT 0x00000003
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# define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000
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# define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001
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# define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002
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# define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003
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# define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000
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# define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001
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# define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002
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# define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003
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#define NV04_FIFO_DATA 0x0010020c
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# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
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# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
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2006-10-10 16:28:15 -06:00
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#define NV03_PGRAPH_STATUS 0x004006b0
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#define NV04_PGRAPH_STATUS 0x00400700
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2006-08-26 16:55:02 -06:00
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#define NV_RAMIN 0x00700000
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#define NV_RAMHT_HANDLE_OFFSET 0
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#define NV_RAMHT_CONTEXT_OFFSET 4
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# define NV_RAMHT_CONTEXT_VALID (1<<31)
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# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
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# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
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# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0
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# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
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# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
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# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
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# define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20
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# define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0
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#define NV_DMA_ACCESS_RW 0
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#define NV_DMA_ACCESS_RO 1
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#define NV_DMA_ACCESS_WO 2
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#define NV_DMA_TARGET_VIDMEM 0
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#define NV_DMA_TARGET_AGP 3
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#define NV03_FIFO_SIZE 0x8000
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#define NV_MAX_FIFO_NUMBER 32
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#define NV03_FIFO_REGS_SIZE 0x10000
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#define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE)
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# define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)
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# define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)
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#define NV_PMC_INTSTAT 0x00000100
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# define NV_PMC_INTSTAT_PFIFO_PENDING (1<< 8)
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# define NV_PMC_INTSTAT_PGRAPH_PENDING (1<<12)
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# define NV_PMC_INTSTAT_CRTC0_PENDING (1<<24)
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# define NV_PMC_INTSTAT_CRTC1_PENDING (1<<25)
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# define NV_PMC_INTSTAT_CRTCn_PENDING (3<<24)
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#define NV_PMC_INTEN 0x00000140
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# define NV_PMC_INTEN_MASTER_ENABLE (1<< 0)
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#define NV_PGRAPH_INTSTAT 0x00400100
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2006-10-10 16:28:15 -06:00
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#define NV04_PGRAPH_INTEN 0x00400140
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#define NV40_PGRAPH_INTEN 0x0040013C
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2006-08-26 16:55:02 -06:00
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# define NV_PGRAPH_INTR_NOTIFY (1<< 0)
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# define NV_PGRAPH_INTR_MISSING_HW (1<< 4)
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2006-10-10 16:28:15 -06:00
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# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)
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2006-08-26 16:55:02 -06:00
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# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)
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# define NV_PGRAPH_INTR_ERROR (1<<20)
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2006-10-10 16:28:15 -06:00
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#define NV_PGRAPH_CTX_CONTROL 0x00400144
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2006-08-26 16:55:02 -06:00
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#define NV_PGRAPH_NV40_UNK220 0x00400220
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# define NV_PGRAPH_NV40_UNK220_FB_INSTANCE
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2006-10-10 16:28:15 -06:00
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#define NV_PGRAPH_CTX_USER 0x00400148
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#define NV_PGRAPH_CTX_SWITCH1 0x0040014C
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#define NV_PGRAPH_FIFO 0x00400720
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#define NV_PGRAPH_FFINTFC_ST2 0x00400764
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2006-08-26 16:55:02 -06:00
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/* It's a guess that this works on NV03. Confirmed on NV04, though */
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2006-10-10 16:28:15 -06:00
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#define NV_PFIFO_DELAY_0 0x00002040
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#define NV_PFIFO_DMA_TIMESLICE 0x00002044
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2006-08-26 16:55:02 -06:00
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#define NV_PFIFO_INTSTAT 0x00002100
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#define NV_PFIFO_INTEN 0x00002140
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2006-10-12 09:31:49 -06:00
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# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
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# define NV_PFIFO_INTR_RUNOUT (1<< 4)
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# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)
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# define NV_PFIFO_INTR_DMA_PUSHER (1<<12)
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# define NV_PFIFO_INTR_DMA_PT (1<<16)
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# define NV_PFIFO_INTR_SEMAPHORE (1<<20)
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# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)
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2006-08-26 16:55:02 -06:00
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#define NV_PFIFO_RAMHT 0x00002210
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#define NV_PFIFO_RAMFC 0x00002214
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#define NV_PFIFO_RAMRO 0x00002218
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#define NV_PFIFO_CACHES 0x00002500
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#define NV_PFIFO_MODE 0x00002504
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2006-10-10 16:28:15 -06:00
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#define NV_PFIFO_DMA 0x00002508
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2006-08-26 16:55:02 -06:00
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#define NV_PFIFO_SIZE 0x0000250c
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#define NV_PFIFO_CACH0_PSH0 0x00003000
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#define NV_PFIFO_CACH0_PUL0 0x00003050
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#define NV_PFIFO_CACH0_PUL1 0x00003054
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#define NV_PFIFO_CACH1_PSH0 0x00003200
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#define NV_PFIFO_CACH1_PSH1 0x00003204
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2006-10-10 16:28:15 -06:00
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#define NV_PFIFO_CACH1_DMAPSH 0x00003220
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2006-08-26 16:55:02 -06:00
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#define NV_PFIFO_CACH1_DMAF 0x00003224
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2006-10-10 16:28:15 -06:00
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# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000
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# define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008
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# define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010
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# define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018
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# define NV_PFIFO_CACH1_DMAF_TRIG_40_BYTES 0x00000020
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# define NV_PFIFO_CACH1_DMAF_TRIG_48_BYTES 0x00000028
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# define NV_PFIFO_CACH1_DMAF_TRIG_56_BYTES 0x00000030
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# define NV_PFIFO_CACH1_DMAF_TRIG_64_BYTES 0x00000038
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# define NV_PFIFO_CACH1_DMAF_TRIG_72_BYTES 0x00000040
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# define NV_PFIFO_CACH1_DMAF_TRIG_80_BYTES 0x00000048
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# define NV_PFIFO_CACH1_DMAF_TRIG_88_BYTES 0x00000050
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# define NV_PFIFO_CACH1_DMAF_TRIG_96_BYTES 0x00000058
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# define NV_PFIFO_CACH1_DMAF_TRIG_104_BYTES 0x00000060
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# define NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES 0x00000068
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# define NV_PFIFO_CACH1_DMAF_TRIG_120_BYTES 0x00000070
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# define NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES 0x00000078
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# define NV_PFIFO_CACH1_DMAF_TRIG_136_BYTES 0x00000080
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# define NV_PFIFO_CACH1_DMAF_TRIG_144_BYTES 0x00000088
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# define NV_PFIFO_CACH1_DMAF_TRIG_152_BYTES 0x00000090
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# define NV_PFIFO_CACH1_DMAF_TRIG_160_BYTES 0x00000098
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# define NV_PFIFO_CACH1_DMAF_TRIG_168_BYTES 0x000000A0
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# define NV_PFIFO_CACH1_DMAF_TRIG_176_BYTES 0x000000A8
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# define NV_PFIFO_CACH1_DMAF_TRIG_184_BYTES 0x000000B0
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# define NV_PFIFO_CACH1_DMAF_TRIG_192_BYTES 0x000000B8
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# define NV_PFIFO_CACH1_DMAF_TRIG_200_BYTES 0x000000C0
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# define NV_PFIFO_CACH1_DMAF_TRIG_208_BYTES 0x000000C8
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# define NV_PFIFO_CACH1_DMAF_TRIG_216_BYTES 0x000000D0
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# define NV_PFIFO_CACH1_DMAF_TRIG_224_BYTES 0x000000D8
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# define NV_PFIFO_CACH1_DMAF_TRIG_232_BYTES 0x000000E0
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# define NV_PFIFO_CACH1_DMAF_TRIG_240_BYTES 0x000000E8
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# define NV_PFIFO_CACH1_DMAF_TRIG_248_BYTES 0x000000F0
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# define NV_PFIFO_CACH1_DMAF_TRIG_256_BYTES 0x000000F8
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# define NV_PFIFO_CACH1_DMAF_SIZE 0x0000E000
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# define NV_PFIFO_CACH1_DMAF_SIZE_32_BYTES 0x00000000
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# define NV_PFIFO_CACH1_DMAF_SIZE_64_BYTES 0x00002000
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# define NV_PFIFO_CACH1_DMAF_SIZE_96_BYTES 0x00004000
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# define NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES 0x00006000
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# define NV_PFIFO_CACH1_DMAF_SIZE_160_BYTES 0x00008000
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# define NV_PFIFO_CACH1_DMAF_SIZE_192_BYTES 0x0000A000
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# define NV_PFIFO_CACH1_DMAF_SIZE_224_BYTES 0x0000C000
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# define NV_PFIFO_CACH1_DMAF_SIZE_256_BYTES 0x0000E000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS 0x001F0000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_0 0x00000000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_1 0x00010000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_2 0x00020000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_3 0x00030000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_4 0x00040000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_5 0x00050000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_6 0x00060000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_7 0x00070000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_8 0x00080000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_9 0x00090000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_10 0x000A0000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_11 0x000B0000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_12 0x000C0000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_13 0x000D0000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_14 0x000E0000
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# define NV_PFIFO_CACH1_DMAF_MAX_REQS_15 0x000F0000
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# define NV_PFIFO_CACH1_ENDIAN 0x80000000
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# define NV_PFIFO_CACH1_LITTLE_ENDIAN 0x7FFFFFFF
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# define NV_PFIFO_CACH1_BIG_ENDIAN 0x80000000
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#define NV_PFIFO_CACH1_DMAS 0x00003228
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2006-08-26 16:55:02 -06:00
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#define NV_PFIFO_CACH1_DMAI 0x0000322c
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#define NV_PFIFO_CACH1_DMAC 0x00003230
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#define NV_PFIFO_CACH1_DMAP 0x00003240
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#define NV_PFIFO_CACH1_DMAG 0x00003244
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#define NV_PFIFO_CACH1_PUL0 0x00003250
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#define NV_PFIFO_CACH1_PUL1 0x00003254
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#define NV_PFIFO_CACH1_HASH 0x00003258
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#define NV_PFIFO_CACH1_ENG 0x00003280
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#define NV_CRTC0_INTSTAT 0x00600100
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#define NV_CRTC0_INTEN 0x00600140
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#define NV_CRTC1_INTSTAT 0x00602100
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#define NV_CRTC1_INTEN 0x00602140
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# define NV_CRTC_INTR_VBLANK (1<<0)
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/* Fifo commands. These are not regs, neither masks */
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#define NV03_FIFO_CMD_JUMP 0x20000000
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#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc
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#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
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2006-10-16 13:12:18 -06:00
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/* RAMFC offsets */
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#define NV40_RAMFC_DMA_PUT 0x00
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#define NV40_RAMFC_DMA_GET 0x04
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#define NV40_RAMFC_REF_CNT 0x08
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#define NV40_RAMFC_DMA_INSTANCE 0x0C
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#define NV40_RAMFC_DMA_DCOUNT /* ? */ 0x10
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#define NV40_RAMFC_DMA_STATE 0x14
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#define NV40_RAMFC_DMA_FETCH 0x18
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#define NV40_RAMFC_ENGINE 0x1C
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#define NV40_RAMFC_PULL1_ENGINE 0x20
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#define NV40_RAMFC_ACQUIRE_VALUE 0x24
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#define NV40_RAMFC_ACQUIRE_TIMESTAMP 0x28
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#define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C
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#define NV40_RAMFC_SEMAPHORE 0x30
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#define NV40_RAMFC_DMA_SUBROUTINE 0x34
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2006-10-16 13:37:40 -06:00
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#define NV40_RAMFC_GRCTX_INSTANCE /* guess */ 0x38
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2006-10-16 13:12:18 -06:00
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#define NV40_RAMFC_DMA_TIMESLICE 0x3C
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#define NV40_RAMFC_UNK_40 0x40
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#define NV40_RAMFC_UNK_44 0x44
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#define NV40_RAMFC_UNK_48 0x48
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#define NV40_RAMFC_2088 0x4C
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#define NV40_RAMFC_3300 0x50
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2006-10-10 16:28:15 -06:00
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