2005-07-27 14:20:30 -06:00
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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2004-06-10 06:45:38 -06:00
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*/
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2005-11-28 16:10:41 -07:00
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/*
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2004-06-10 06:45:38 -06:00
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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2005-06-06 03:18:44 -06:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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2005-11-28 16:10:41 -07:00
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*/
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2004-06-10 06:45:38 -06:00
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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2005-12-28 16:49:59 -07:00
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#define USER_INT_FLAG (1<<1)
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#define VSYNC_PIPEB_FLAG (1<<5)
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#define VSYNC_PIPEA_FLAG (1<<7)
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2004-06-10 06:45:38 -06:00
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#define MAX_NOPID ((u32)~0)
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2007-02-22 09:21:18 -07:00
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/**
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* Emit a synchronous flip.
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*
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* This function must be called with the drawable spinlock held.
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*/
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static void
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i915_dispatch_vsync_flip(drm_device_t *dev, drm_drawable_info_t *drw, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
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u16 x1, y1, x2, y2;
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int pf_pipes = 1 << pipe;
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/* If the window is visible on the other pipe, we have to flip on that
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* pipe as well.
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*/
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if (pipe == 1) {
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x1 = sarea_priv->pipeA_x;
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y1 = sarea_priv->pipeA_y;
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x2 = x1 + sarea_priv->pipeA_w;
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y2 = y1 + sarea_priv->pipeA_h;
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} else {
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x1 = sarea_priv->pipeB_x;
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y1 = sarea_priv->pipeB_y;
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x2 = x1 + sarea_priv->pipeB_w;
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y2 = y1 + sarea_priv->pipeB_h;
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}
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if (x2 > 0 && y2 > 0) {
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int i, num_rects = drw->num_rects;
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drm_clip_rect_t *rect = drw->rects;
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for (i = 0; i < num_rects; i++)
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if (!((rect[i].x1 > x2 && rect[i].y1 > y2) ||
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(rect[i].x2 < x1 && rect[i].y2 < y1))) {
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pf_pipes = 0x3;
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break;
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}
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}
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i915_dispatch_flip(dev, pf_pipes, 1);
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}
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2006-08-25 11:01:05 -06:00
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/**
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* Emit blits for scheduled buffer swaps.
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*
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* This function will be called with the HW lock held.
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*/
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static void i915_vblank_tasklet(drm_device_t *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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2006-10-02 07:33:19 -06:00
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unsigned long irqflags;
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2006-10-26 05:15:30 -06:00
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struct list_head *list, *tmp, hits, *hit;
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2007-02-19 04:27:54 -07:00
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int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
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2006-10-26 05:15:30 -06:00
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unsigned counter[2] = { atomic_read(&dev->vbl_received),
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atomic_read(&dev->vbl_received2) };
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drm_drawable_info_t *drw;
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drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
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2007-02-19 04:27:54 -07:00
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u32 cpp = dev_priv->cpp, offsets[3];
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2006-10-26 05:15:30 -06:00
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u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
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XY_SRC_COPY_BLT_WRITE_ALPHA |
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XY_SRC_COPY_BLT_WRITE_RGB)
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: XY_SRC_COPY_BLT_CMD;
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u32 pitchropcpp = (sarea_priv->pitch * cpp) | (0xcc << 16) |
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(cpp << 23) | (1 << 24);
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RING_LOCALS;
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2006-08-25 11:01:05 -06:00
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DRM_DEBUG("\n");
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2006-10-26 05:15:30 -06:00
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INIT_LIST_HEAD(&hits);
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nhits = nrects = 0;
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2006-08-25 11:01:05 -06:00
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spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
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2006-10-26 05:15:30 -06:00
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/* Find buffer swaps scheduled for this vertical blank */
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2006-08-25 11:01:05 -06:00
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list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
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drm_i915_vbl_swap_t *vbl_swap =
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list_entry(list, drm_i915_vbl_swap_t, head);
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2006-10-26 05:15:30 -06:00
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if ((counter[vbl_swap->pipe] - vbl_swap->sequence) > (1<<23))
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continue;
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list_del(list);
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dev_priv->swaps_pending--;
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spin_unlock(&dev_priv->swaps_lock);
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spin_lock(&dev->drw_lock);
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2006-08-25 11:01:05 -06:00
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2006-10-26 05:15:30 -06:00
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drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
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2006-08-25 11:01:05 -06:00
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2006-10-26 05:15:30 -06:00
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if (!drw) {
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spin_unlock(&dev->drw_lock);
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drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
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spin_lock(&dev_priv->swaps_lock);
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continue;
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}
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2006-08-25 11:01:05 -06:00
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2006-10-26 05:15:30 -06:00
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list_for_each(hit, &hits) {
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drm_i915_vbl_swap_t *swap_cmp =
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list_entry(hit, drm_i915_vbl_swap_t, head);
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drm_drawable_info_t *drw_cmp =
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drm_get_drawable_info(dev, swap_cmp->drw_id);
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2006-08-25 11:01:05 -06:00
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2006-10-26 05:15:30 -06:00
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if (drw_cmp &&
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drw_cmp->rects[0].y1 > drw->rects[0].y1) {
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list_add_tail(list, hit);
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break;
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2006-08-25 11:01:05 -06:00
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}
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2006-10-26 05:15:30 -06:00
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}
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2006-08-25 11:01:05 -06:00
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2006-10-26 05:15:30 -06:00
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spin_unlock(&dev->drw_lock);
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2006-08-25 11:01:05 -06:00
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2006-10-26 05:15:30 -06:00
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/* List of hits was empty, or we reached the end of it */
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if (hit == &hits)
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list_add_tail(list, hits.prev);
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2006-08-25 11:01:05 -06:00
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2006-10-26 05:15:30 -06:00
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nhits++;
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2006-08-25 11:01:05 -06:00
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2006-10-26 05:15:30 -06:00
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spin_lock(&dev_priv->swaps_lock);
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}
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if (nhits == 0) {
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spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
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return;
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}
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spin_unlock(&dev_priv->swaps_lock);
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i915_kernel_lost_context(dev);
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upper[0] = upper[1] = 0;
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slice[0] = max(sarea_priv->pipeA_h / nhits, 1);
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slice[1] = max(sarea_priv->pipeB_h / nhits, 1);
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lower[0] = sarea_priv->pipeA_y + slice[0];
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lower[1] = sarea_priv->pipeB_y + slice[0];
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2007-02-19 04:27:54 -07:00
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offsets[0] = sarea_priv->front_offset;
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offsets[1] = sarea_priv->back_offset;
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offsets[2] = sarea_priv->third_offset;
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num_pages = sarea_priv->third_handle ? 3 : 2;
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2006-10-26 05:15:30 -06:00
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spin_lock(&dev->drw_lock);
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/* Emit blits for buffer swaps, partitioning both outputs into as many
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* slices as there are buffer swaps scheduled in order to avoid tearing
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* (based on the assumption that a single buffer swap would always
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* complete before scanout starts).
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*/
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for (i = 0; i++ < nhits;
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upper[0] = lower[0], lower[0] += slice[0],
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upper[1] = lower[1], lower[1] += slice[1]) {
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2007-02-22 09:21:18 -07:00
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int init_drawrect = 1;
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2006-10-26 05:15:30 -06:00
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if (i == nhits)
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lower[0] = lower[1] = sarea_priv->height;
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list_for_each(hit, &hits) {
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drm_i915_vbl_swap_t *swap_hit =
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list_entry(hit, drm_i915_vbl_swap_t, head);
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drm_clip_rect_t *rect;
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2007-02-19 04:27:54 -07:00
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int num_rects, pipe, front, back;
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2006-10-26 05:15:30 -06:00
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unsigned short top, bottom;
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drw = drm_get_drawable_info(dev, swap_hit->drw_id);
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if (!drw)
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continue;
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pipe = swap_hit->pipe;
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2007-02-22 09:21:18 -07:00
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if (swap_hit->flip) {
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i915_dispatch_vsync_flip(dev, drw, pipe);
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continue;
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}
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if (init_drawrect) {
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BEGIN_LP_RING(6);
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OUT_RING(GFX_OP_DRAWRECT_INFO);
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OUT_RING(0);
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OUT_RING(0);
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OUT_RING(sarea_priv->width | sarea_priv->height << 16);
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OUT_RING(sarea_priv->width | sarea_priv->height << 16);
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OUT_RING(0);
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ADVANCE_LP_RING();
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sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
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init_drawrect = 0;
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}
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rect = drw->rects;
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2006-10-26 05:15:30 -06:00
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top = upper[pipe];
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bottom = lower[pipe];
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2007-02-19 04:27:54 -07:00
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front = (dev_priv->current_page >> (2 * pipe)) & 0x3;
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back = (front + 1) % num_pages;
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2006-10-26 05:15:30 -06:00
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for (num_rects = drw->num_rects; num_rects--; rect++) {
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int y1 = max(rect->y1, top);
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int y2 = min(rect->y2, bottom);
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if (y1 >= y2)
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continue;
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BEGIN_LP_RING(8);
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OUT_RING(cmd);
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OUT_RING(pitchropcpp);
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OUT_RING((y1 << 16) | rect->x1);
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OUT_RING((y2 << 16) | rect->x2);
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2007-02-19 04:27:54 -07:00
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OUT_RING(offsets[front]);
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2006-10-26 05:15:30 -06:00
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OUT_RING((y1 << 16) | rect->x1);
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OUT_RING(pitchropcpp & 0xffff);
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2007-02-19 04:27:54 -07:00
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OUT_RING(offsets[back]);
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2006-10-26 05:15:30 -06:00
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ADVANCE_LP_RING();
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}
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2006-08-25 11:01:05 -06:00
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}
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}
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2006-10-26 05:15:30 -06:00
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spin_unlock_irqrestore(&dev->drw_lock, irqflags);
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list_for_each_safe(hit, tmp, &hits) {
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drm_i915_vbl_swap_t *swap_hit =
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list_entry(hit, drm_i915_vbl_swap_t, head);
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list_del(hit);
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drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
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}
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2006-08-25 11:01:05 -06:00
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}
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2004-08-27 03:14:30 -06:00
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irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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2004-06-10 06:45:38 -06:00
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{
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2004-08-27 03:14:30 -06:00
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drm_device_t *dev = (drm_device_t *) arg;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u16 temp;
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2007-01-24 01:33:21 -07:00
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u32 pipea_stats, pipeb_stats;
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2004-06-10 06:45:38 -06:00
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2007-01-24 01:33:21 -07:00
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pipea_stats = I915_READ(I915REG_PIPEASTAT);
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pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
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2004-08-27 03:14:30 -06:00
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temp = I915_READ16(I915REG_INT_IDENTITY_R);
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2006-09-15 03:18:35 -06:00
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temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG);
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2004-08-27 03:14:30 -06:00
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2006-09-12 04:01:00 -06:00
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#if 0
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2004-06-10 06:45:38 -06:00
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DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
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2006-09-12 04:01:00 -06:00
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#endif
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2004-08-27 03:14:30 -06:00
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if (temp == 0)
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2004-06-10 06:45:38 -06:00
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return IRQ_NONE;
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2004-08-27 03:14:30 -06:00
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I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
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2005-12-28 16:49:59 -07:00
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2006-02-09 16:14:16 -07:00
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dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
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2006-08-21 13:36:00 -06:00
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if (temp & USER_INT_FLAG) {
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2005-12-28 16:49:59 -07:00
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DRM_WAKEUP(&dev_priv->irq_queue);
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2006-08-21 13:36:00 -06:00
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#ifdef I915_HAVE_FENCE
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i915_fence_handler(dev);
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#endif
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}
|
2005-12-28 16:49:59 -07:00
|
|
|
|
2006-06-19 14:15:53 -06:00
|
|
|
if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) {
|
2006-09-27 10:22:10 -06:00
|
|
|
int vblank_pipe = dev_priv->vblank_pipe;
|
|
|
|
|
|
|
|
if ((vblank_pipe &
|
2006-08-11 10:06:46 -06:00
|
|
|
(DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
|
|
|
|
== (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
|
|
|
|
if (temp & VSYNC_PIPEA_FLAG)
|
|
|
|
atomic_inc(&dev->vbl_received);
|
|
|
|
if (temp & VSYNC_PIPEB_FLAG)
|
|
|
|
atomic_inc(&dev->vbl_received2);
|
2006-09-27 10:22:10 -06:00
|
|
|
} else if (((temp & VSYNC_PIPEA_FLAG) &&
|
|
|
|
(vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
|
|
|
|
((temp & VSYNC_PIPEB_FLAG) &&
|
|
|
|
(vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
|
2006-08-11 10:06:46 -06:00
|
|
|
atomic_inc(&dev->vbl_received);
|
|
|
|
|
2005-12-28 16:49:59 -07:00
|
|
|
DRM_WAKEUP(&dev->vbl_queue);
|
|
|
|
drm_vbl_send_signals(dev);
|
2006-08-25 11:01:05 -06:00
|
|
|
|
2006-09-29 02:27:29 -06:00
|
|
|
if (dev_priv->swaps_pending > 0)
|
|
|
|
drm_locked_tasklet(dev, i915_vblank_tasklet);
|
2007-01-24 01:33:21 -07:00
|
|
|
I915_WRITE(I915REG_PIPEASTAT,
|
|
|
|
pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
|
|
|
|
I915_VBLANK_CLEAR);
|
|
|
|
I915_WRITE(I915REG_PIPEBSTAT,
|
|
|
|
pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
|
|
|
|
I915_VBLANK_CLEAR);
|
2005-12-28 16:49:59 -07:00
|
|
|
}
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2006-08-21 13:36:00 -06:00
|
|
|
int i915_emit_irq(drm_device_t * dev)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2006-08-08 16:05:54 -06:00
|
|
|
|
2006-08-09 22:38:50 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
RING_LOCALS;
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2006-08-09 22:38:50 -06:00
|
|
|
i915_kernel_lost_context(dev);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2006-08-09 22:38:50 -06:00
|
|
|
DRM_DEBUG("%s\n", __FUNCTION__);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2007-02-02 09:23:42 -07:00
|
|
|
i915_emit_breadcrumb(dev);
|
2006-08-08 16:05:54 -06:00
|
|
|
|
2007-02-02 09:23:42 -07:00
|
|
|
BEGIN_LP_RING(2);
|
2006-08-09 22:38:50 -06:00
|
|
|
OUT_RING(0);
|
|
|
|
OUT_RING(GFX_OP_USER_INTERRUPT);
|
|
|
|
ADVANCE_LP_RING();
|
2006-08-08 16:05:54 -06:00
|
|
|
|
2006-08-09 22:38:50 -06:00
|
|
|
return dev_priv->counter;
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2006-09-05 06:23:18 -06:00
|
|
|
void i915_user_irq_on(drm_i915_private_t *dev_priv)
|
|
|
|
{
|
|
|
|
spin_lock(&dev_priv->user_irq_lock);
|
2006-09-08 09:24:38 -06:00
|
|
|
if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
|
2006-09-05 06:23:18 -06:00
|
|
|
dev_priv->irq_enable_reg |= USER_INT_FLAG;
|
|
|
|
I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
|
|
|
|
}
|
|
|
|
spin_unlock(&dev_priv->user_irq_lock);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_user_irq_off(drm_i915_private_t *dev_priv)
|
|
|
|
{
|
|
|
|
spin_lock(&dev_priv->user_irq_lock);
|
|
|
|
if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
|
2006-09-28 11:13:59 -06:00
|
|
|
// dev_priv->irq_enable_reg &= ~USER_INT_FLAG;
|
2006-09-15 03:18:35 -06:00
|
|
|
// I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
|
2006-09-05 06:23:18 -06:00
|
|
|
}
|
|
|
|
spin_unlock(&dev_priv->user_irq_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-02-01 03:43:42 -07:00
|
|
|
static int i915_wait_irq(drm_device_t * dev, int irq_nr)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2004-06-10 06:45:38 -06:00
|
|
|
int ret = 0;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_DEBUG("%s irq_nr=%d breadcrumb=%d\n", __FUNCTION__, irq_nr,
|
|
|
|
READ_BREADCRUMB(dev_priv));
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (READ_BREADCRUMB(dev_priv) >= irq_nr)
|
|
|
|
return 0;
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
|
2006-09-05 06:23:18 -06:00
|
|
|
|
|
|
|
i915_user_irq_on(dev_priv);
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
|
|
|
|
READ_BREADCRUMB(dev_priv) >= irq_nr);
|
2006-09-05 06:23:18 -06:00
|
|
|
i915_user_irq_off(dev_priv);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
if (ret == DRM_ERR(EBUSY)) {
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_ERROR("%s: EBUSY -- rec: %d emitted: %d\n",
|
2004-06-10 06:45:38 -06:00
|
|
|
__FUNCTION__,
|
2004-08-27 03:14:30 -06:00
|
|
|
READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
2004-06-10 06:45:38 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2006-08-11 10:06:46 -06:00
|
|
|
static int i915_driver_vblank_do_wait(drm_device_t *dev, unsigned int *sequence,
|
|
|
|
atomic_t *counter)
|
2005-12-28 16:49:59 -07:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
unsigned int cur_vblank;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (!dev_priv) {
|
|
|
|
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
|
2006-08-11 10:06:46 -06:00
|
|
|
(((cur_vblank = atomic_read(counter))
|
2005-12-28 16:49:59 -07:00
|
|
|
- *sequence) <= (1<<23)));
|
|
|
|
|
|
|
|
*sequence = cur_vblank;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2006-08-11 10:06:46 -06:00
|
|
|
int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
|
|
|
|
{
|
|
|
|
return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
|
|
|
|
}
|
|
|
|
|
|
|
|
int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence)
|
|
|
|
{
|
|
|
|
return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
|
|
|
|
}
|
|
|
|
|
2004-06-10 06:45:38 -06:00
|
|
|
/* Needs the lock as it touches the ring.
|
|
|
|
*/
|
2004-08-27 03:14:30 -06:00
|
|
|
int i915_irq_emit(DRM_IOCTL_ARGS)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_i915_irq_emit_t emit;
|
|
|
|
int result;
|
|
|
|
|
2004-11-11 04:09:11 -07:00
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (!dev_priv) {
|
|
|
|
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
2004-06-10 06:45:38 -06:00
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(emit, (drm_i915_irq_emit_t __user *) data,
|
|
|
|
sizeof(emit));
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
result = i915_emit_irq(dev);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) {
|
|
|
|
DRM_ERROR("copy_to_user\n");
|
2004-06-10 06:45:38 -06:00
|
|
|
return DRM_ERR(EFAULT);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Doesn't need the hardware lock.
|
|
|
|
*/
|
2004-08-27 03:14:30 -06:00
|
|
|
int i915_irq_wait(DRM_IOCTL_ARGS)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_i915_irq_wait_t irqwait;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (!dev_priv) {
|
|
|
|
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
2004-06-10 06:45:38 -06:00
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_i915_irq_wait_t __user *) data,
|
|
|
|
sizeof(irqwait));
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
return i915_wait_irq(dev, irqwait.irq_seq);
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|
|
|
|
|
2006-08-31 10:30:55 -06:00
|
|
|
static void i915_enable_interrupt (drm_device_t *dev)
|
2006-06-20 18:15:10 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
|
2006-10-18 09:33:19 -06:00
|
|
|
dev_priv->irq_enable_reg = USER_INT_FLAG;
|
2006-06-20 18:15:10 -06:00
|
|
|
if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
|
2006-09-28 11:13:59 -06:00
|
|
|
dev_priv->irq_enable_reg |= VSYNC_PIPEA_FLAG;
|
2006-06-20 18:15:10 -06:00
|
|
|
if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
|
2006-09-28 11:13:59 -06:00
|
|
|
dev_priv->irq_enable_reg |= VSYNC_PIPEB_FLAG;
|
2006-08-31 10:30:55 -06:00
|
|
|
|
2006-09-28 11:13:59 -06:00
|
|
|
I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
|
2006-09-05 06:23:18 -06:00
|
|
|
dev_priv->irq_enabled = 1;
|
2006-06-20 18:15:10 -06:00
|
|
|
}
|
|
|
|
|
2006-06-19 14:15:53 -06:00
|
|
|
/* Set the vblank monitor pipe
|
|
|
|
*/
|
|
|
|
int i915_vblank_pipe_set(DRM_IOCTL_ARGS)
|
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_i915_vblank_pipe_t pipe;
|
|
|
|
|
|
|
|
if (!dev_priv) {
|
|
|
|
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(pipe, (drm_i915_vblank_pipe_t __user *) data,
|
|
|
|
sizeof(pipe));
|
|
|
|
|
2006-08-31 10:30:55 -06:00
|
|
|
if (pipe.pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
|
|
|
|
DRM_ERROR("%s called with invalid pipe 0x%x\n",
|
|
|
|
__FUNCTION__, pipe.pipe);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2006-06-20 18:15:10 -06:00
|
|
|
dev_priv->vblank_pipe = pipe.pipe;
|
2006-08-31 10:30:55 -06:00
|
|
|
|
|
|
|
i915_enable_interrupt (dev);
|
|
|
|
|
|
|
|
return 0;
|
2006-06-19 14:15:53 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
int i915_vblank_pipe_get(DRM_IOCTL_ARGS)
|
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_i915_vblank_pipe_t pipe;
|
|
|
|
u16 flag;
|
|
|
|
|
|
|
|
if (!dev_priv) {
|
|
|
|
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
flag = I915_READ(I915REG_INT_ENABLE_R);
|
|
|
|
pipe.pipe = 0;
|
|
|
|
if (flag & VSYNC_PIPEA_FLAG)
|
|
|
|
pipe.pipe |= DRM_I915_VBLANK_PIPE_A;
|
|
|
|
if (flag & VSYNC_PIPEB_FLAG)
|
|
|
|
pipe.pipe |= DRM_I915_VBLANK_PIPE_B;
|
|
|
|
DRM_COPY_TO_USER_IOCTL((drm_i915_vblank_pipe_t __user *) data, pipe,
|
|
|
|
sizeof(pipe));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-08-25 11:01:05 -06:00
|
|
|
/**
|
|
|
|
* Schedule buffer swap at given vertical blank.
|
|
|
|
*/
|
|
|
|
int i915_vblank_swap(DRM_IOCTL_ARGS)
|
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_i915_vblank_swap_t swap;
|
|
|
|
drm_i915_vbl_swap_t *vbl_swap;
|
2006-10-02 07:33:19 -06:00
|
|
|
unsigned int pipe, seqtype, curseq;
|
|
|
|
unsigned long irqflags;
|
2006-08-25 11:01:05 -06:00
|
|
|
struct list_head *list;
|
|
|
|
|
|
|
|
if (!dev_priv) {
|
|
|
|
DRM_ERROR("%s called with no initialization\n", __func__);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_priv->sarea_priv->rotation) {
|
|
|
|
DRM_DEBUG("Rotation not supported\n");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(swap, (drm_i915_vblank_swap_t __user *) data,
|
|
|
|
sizeof(swap));
|
|
|
|
|
2006-08-30 11:33:28 -06:00
|
|
|
if (swap.seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
|
2007-02-22 09:21:18 -07:00
|
|
|
_DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
|
|
|
|
_DRM_VBLANK_FLIP)) {
|
2006-08-30 11:33:28 -06:00
|
|
|
DRM_ERROR("Invalid sequence type 0x%x\n", swap.seqtype);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
pipe = (swap.seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
|
|
|
|
|
|
|
|
seqtype = swap.seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
|
|
|
|
|
|
|
|
if (!(dev_priv->vblank_pipe & (1 << pipe))) {
|
|
|
|
DRM_ERROR("Invalid pipe %d\n", pipe);
|
2006-08-25 11:01:05 -06:00
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->drw_lock, irqflags);
|
|
|
|
|
|
|
|
if (!drm_get_drawable_info(dev, swap.drawable)) {
|
|
|
|
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
2007-01-02 02:05:48 -07:00
|
|
|
DRM_DEBUG("Invalid drawable ID %d\n", swap.drawable);
|
2006-08-25 11:01:05 -06:00
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
|
|
|
|
2006-08-30 11:33:28 -06:00
|
|
|
curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received);
|
|
|
|
|
2006-09-13 00:59:35 -06:00
|
|
|
if (seqtype == _DRM_VBLANK_RELATIVE)
|
2006-08-30 11:33:28 -06:00
|
|
|
swap.sequence += curseq;
|
2006-09-13 00:59:35 -06:00
|
|
|
|
|
|
|
if ((curseq - swap.sequence) <= (1<<23)) {
|
|
|
|
if (swap.seqtype & _DRM_VBLANK_NEXTONMISS) {
|
|
|
|
swap.sequence = curseq + 1;
|
|
|
|
} else {
|
2006-08-30 11:33:28 -06:00
|
|
|
DRM_DEBUG("Missed target sequence\n");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-02-22 09:21:18 -07:00
|
|
|
if (swap.seqtype & _DRM_VBLANK_FLIP) {
|
|
|
|
swap.sequence--;
|
|
|
|
|
|
|
|
if ((curseq - swap.sequence) <= (1<<23)) {
|
|
|
|
drm_drawable_info_t *drw;
|
|
|
|
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->drw_lock, irqflags);
|
|
|
|
|
|
|
|
drw = drm_get_drawable_info(dev, swap.drawable);
|
|
|
|
|
|
|
|
if (!drw) {
|
|
|
|
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
|
|
|
DRM_DEBUG("Invalid drawable ID %d\n",
|
|
|
|
swap.drawable);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
i915_dispatch_vsync_flip(dev, drw, pipe);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-09-13 00:59:35 -06:00
|
|
|
spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
|
|
|
|
|
2006-08-25 11:01:05 -06:00
|
|
|
list_for_each(list, &dev_priv->vbl_swaps.head) {
|
|
|
|
vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
|
|
|
|
|
|
|
|
if (vbl_swap->drw_id == swap.drawable &&
|
2006-08-30 11:33:28 -06:00
|
|
|
vbl_swap->pipe == pipe &&
|
2006-08-25 11:01:05 -06:00
|
|
|
vbl_swap->sequence == swap.sequence) {
|
2007-02-22 09:21:18 -07:00
|
|
|
vbl_swap->flip = (swap.seqtype & _DRM_VBLANK_FLIP);
|
2006-08-25 11:01:05 -06:00
|
|
|
spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
|
|
|
|
DRM_DEBUG("Already scheduled\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
|
|
|
|
|
2006-09-01 03:48:07 -06:00
|
|
|
if (dev_priv->swaps_pending >= 100) {
|
|
|
|
DRM_DEBUG("Too many swaps queued\n");
|
|
|
|
return DRM_ERR(EBUSY);
|
|
|
|
}
|
|
|
|
|
2006-08-25 11:01:05 -06:00
|
|
|
vbl_swap = drm_calloc(1, sizeof(vbl_swap), DRM_MEM_DRIVER);
|
|
|
|
|
|
|
|
if (!vbl_swap) {
|
|
|
|
DRM_ERROR("Failed to allocate memory to queue swap\n");
|
|
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG("\n");
|
|
|
|
|
|
|
|
vbl_swap->drw_id = swap.drawable;
|
2006-08-30 11:33:28 -06:00
|
|
|
vbl_swap->pipe = pipe;
|
2006-08-25 11:01:05 -06:00
|
|
|
vbl_swap->sequence = swap.sequence;
|
2007-02-22 09:21:18 -07:00
|
|
|
vbl_swap->flip = (swap.seqtype & _DRM_VBLANK_FLIP);
|
|
|
|
|
|
|
|
if (vbl_swap->flip)
|
|
|
|
swap.sequence++;
|
2006-08-25 11:01:05 -06:00
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
|
|
|
|
|
|
|
|
list_add_tail((struct list_head *)vbl_swap, &dev_priv->vbl_swaps.head);
|
|
|
|
dev_priv->swaps_pending++;
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
|
|
|
|
|
2006-08-30 11:33:28 -06:00
|
|
|
DRM_COPY_TO_USER_IOCTL((drm_i915_vblank_swap_t __user *) data, swap,
|
|
|
|
sizeof(swap));
|
|
|
|
|
2006-08-25 11:01:05 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-06-10 06:45:38 -06:00
|
|
|
/* drm_dma.h hooks
|
|
|
|
*/
|
2004-08-27 03:14:30 -06:00
|
|
|
void i915_driver_irq_preinstall(drm_device_t * dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2006-08-21 13:36:00 -06:00
|
|
|
I915_WRITE16(I915REG_HWSTAM, 0xeffe);
|
2004-08-27 03:14:30 -06:00
|
|
|
I915_WRITE16(I915REG_INT_MASK_R, 0x0);
|
|
|
|
I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
void i915_driver_irq_postinstall(drm_device_t * dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2006-08-25 11:01:05 -06:00
|
|
|
dev_priv->swaps_lock = SPIN_LOCK_UNLOCKED;
|
|
|
|
INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
|
|
|
|
dev_priv->swaps_pending = 0;
|
|
|
|
|
2006-10-18 09:33:19 -06:00
|
|
|
if (!dev_priv->vblank_pipe)
|
|
|
|
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
|
|
|
|
|
|
|
|
dev_priv->swaps_lock = SPIN_LOCK_UNLOCKED;
|
|
|
|
INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
|
|
|
|
dev_priv->swaps_pending = 0;
|
|
|
|
|
2006-09-28 11:13:59 -06:00
|
|
|
dev_priv->user_irq_lock = SPIN_LOCK_UNLOCKED;
|
|
|
|
dev_priv->user_irq_refcount = 0;
|
|
|
|
|
2006-08-31 10:30:55 -06:00
|
|
|
if (!dev_priv->vblank_pipe)
|
|
|
|
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
|
2006-06-20 18:15:10 -06:00
|
|
|
i915_enable_interrupt(dev);
|
2004-06-10 06:45:38 -06:00
|
|
|
DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
|
2006-08-29 10:40:08 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the hardware status page IRQ location.
|
|
|
|
*/
|
|
|
|
|
|
|
|
I915_WRITE(I915REG_INSTPM, ( 1 << 5) | ( 1 << 21));
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
void i915_driver_irq_uninstall(drm_device_t * dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2006-02-17 21:13:36 -07:00
|
|
|
u16 temp;
|
2004-06-10 06:45:38 -06:00
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2006-09-05 06:23:18 -06:00
|
|
|
dev_priv->irq_enabled = 0;
|
2004-08-27 03:14:30 -06:00
|
|
|
I915_WRITE16(I915REG_HWSTAM, 0xffff);
|
|
|
|
I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
|
|
|
|
I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
|
2006-02-17 21:13:36 -07:00
|
|
|
|
|
|
|
temp = I915_READ16(I915REG_INT_IDENTITY_R);
|
2006-03-25 00:16:14 -07:00
|
|
|
I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|