2004-06-10 06:45:38 -06:00
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/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
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*/
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/**************************************************************************
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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**************************************************************************/
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2004-09-27 14:14:31 -06:00
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#include "i915.h"
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2004-06-10 06:45:38 -06:00
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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2004-08-27 03:14:30 -06:00
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static inline void i915_print_status_page(drm_device_t * dev)
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2004-06-10 06:45:38 -06:00
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{
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2004-08-27 03:14:30 -06:00
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drm_i915_private_t *dev_priv = dev->dev_private;
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2004-06-10 06:45:38 -06:00
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u32 *temp = dev_priv->hw_status_page;
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if (!temp) {
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DRM_DEBUG("no status page\n");
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return;
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}
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2004-08-27 03:14:30 -06:00
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DRM_DEBUG("hw_status: Interrupt Status : %x\n", temp[0]);
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DRM_DEBUG("hw_status: LpRing Head ptr : %x\n", temp[1]);
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DRM_DEBUG("hw_status: IRing Head ptr : %x\n", temp[2]);
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DRM_DEBUG("hw_status: Reserved : %x\n", temp[3]);
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DRM_DEBUG("hw_status: Driver Counter : %d\n", temp[5]);
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2004-06-10 06:45:38 -06:00
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}
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/* Really want an OS-independent resettable timer. Would like to have
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* this loop run for (eg) 3 sec, but have the timer reset every time
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* the head pointer changes, so that EBUSY only happens if the ring
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* actually stalls for (eg) 3 seconds.
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*/
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2004-08-27 03:14:30 -06:00
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int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
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2004-06-10 06:45:38 -06:00
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{
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2004-08-27 03:14:30 -06:00
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
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2004-06-10 06:45:38 -06:00
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u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
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int i;
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2004-08-27 03:14:30 -06:00
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for (i = 0; i < 10000; i++) {
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2004-06-10 06:45:38 -06:00
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ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
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2004-08-27 03:14:30 -06:00
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->Size;
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if (ring->space >= n)
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2004-06-10 06:45:38 -06:00
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return 0;
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2004-08-27 03:14:30 -06:00
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2004-06-10 06:45:38 -06:00
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dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
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2004-08-27 03:14:30 -06:00
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if (ring->head != last_head)
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2004-06-10 06:45:38 -06:00
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i = 0;
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last_head = ring->head;
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}
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return DRM_ERR(EBUSY);
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}
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2004-08-27 03:14:30 -06:00
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void i915_kernel_lost_context(drm_device_t * dev)
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2004-06-10 06:45:38 -06:00
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{
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2004-08-27 03:14:30 -06:00
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
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ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
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ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->Size;
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2004-06-10 06:45:38 -06:00
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if (ring->head == ring->tail)
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dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
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}
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2004-08-27 03:14:30 -06:00
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int i915_dma_cleanup(drm_device_t * dev)
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2004-06-10 06:45:38 -06:00
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{
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/* Make sure interrupts are disabled here because the uninstall ioctl
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* may not have been called from userspace and after dev_private
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* is freed, it's too late.
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*/
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2004-08-27 03:14:30 -06:00
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if (dev->irq)
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2004-09-27 14:14:31 -06:00
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DRM(irq_uninstall) (dev);
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2004-06-10 06:45:38 -06:00
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if (dev->dev_private) {
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2004-08-27 03:14:30 -06:00
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drm_i915_private_t *dev_priv =
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(drm_i915_private_t *) dev->dev_private;
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if (dev_priv->ring.virtual_start) {
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drm_core_ioremapfree(&dev_priv->ring.map, dev);
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2004-06-10 06:45:38 -06:00
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}
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2004-08-27 03:14:30 -06:00
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if (dev_priv->hw_status_page) {
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2004-07-29 05:09:22 -06:00
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#ifdef __FreeBSD__
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2004-08-27 03:14:30 -06:00
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#if __FreeBSD_version > 500000
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2004-11-05 18:41:47 -07:00
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contigfree(dev_priv->hw_status_page, PAGE_SIZE, M_DRM);
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2004-07-29 05:09:22 -06:00
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#endif
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#else
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2004-06-10 06:45:38 -06:00
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pci_free_consistent(dev->pdev, PAGE_SIZE,
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2004-08-27 03:14:30 -06:00
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dev_priv->hw_status_page,
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dev_priv->dma_status_page);
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2004-07-29 05:09:22 -06:00
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#endif
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2004-08-27 03:14:30 -06:00
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/* Need to rewrite hardware status page */
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I915_WRITE(0x02080, 0x1ffff000);
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2004-06-10 06:45:38 -06:00
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}
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2004-09-27 14:14:31 -06:00
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DRM(free) (dev->dev_private, sizeof(drm_i915_private_t),
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2004-08-27 03:14:30 -06:00
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DRM_MEM_DRIVER);
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2004-06-10 06:45:38 -06:00
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2004-08-27 03:14:30 -06:00
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dev->dev_private = NULL;
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2004-06-10 06:45:38 -06:00
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}
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2004-08-27 03:14:30 -06:00
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return 0;
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2004-06-10 06:45:38 -06:00
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}
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2004-08-27 03:14:30 -06:00
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static int i915_initialize(drm_device_t * dev,
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drm_i915_private_t * dev_priv,
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drm_i915_init_t * init)
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2004-06-10 06:45:38 -06:00
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{
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2004-08-27 03:14:30 -06:00
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memset(dev_priv, 0, sizeof(drm_i915_private_t));
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2004-06-10 06:45:38 -06:00
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DRM_GETSAREA();
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2004-08-27 03:14:30 -06:00
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if (!dev_priv->sarea) {
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2004-06-10 06:45:38 -06:00
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DRM_ERROR("can not find sarea!\n");
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dev->dev_private = (void *)dev_priv;
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2004-07-29 05:09:22 -06:00
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i915_dma_cleanup(dev);
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2004-06-10 06:45:38 -06:00
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return DRM_ERR(EINVAL);
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}
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2004-08-27 03:14:30 -06:00
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2004-08-17 07:10:05 -06:00
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dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
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2004-08-27 03:14:30 -06:00
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if (!dev_priv->mmio_map) {
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2004-06-10 06:45:38 -06:00
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dev->dev_private = (void *)dev_priv;
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2004-07-29 05:09:22 -06:00
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i915_dma_cleanup(dev);
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2004-06-10 06:45:38 -06:00
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DRM_ERROR("can not find mmio map!\n");
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return DRM_ERR(EINVAL);
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}
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dev_priv->sarea_priv = (drm_i915_sarea_t *)
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2004-08-27 03:14:30 -06:00
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((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
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dev_priv->ring.Start = init->ring_start;
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dev_priv->ring.End = init->ring_end;
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dev_priv->ring.Size = init->ring_size;
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dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
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2004-06-10 06:45:38 -06:00
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dev_priv->ring.map.offset = init->ring_start;
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dev_priv->ring.map.size = init->ring_size;
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dev_priv->ring.map.type = 0;
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dev_priv->ring.map.flags = 0;
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dev_priv->ring.map.mtrr = 0;
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2004-08-27 03:14:30 -06:00
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drm_core_ioremap(&dev_priv->ring.map, dev);
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2004-06-10 06:45:38 -06:00
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2004-08-27 03:14:30 -06:00
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if (dev_priv->ring.map.handle == NULL) {
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dev->dev_private = (void *)dev_priv;
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i915_dma_cleanup(dev);
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DRM_ERROR("can not ioremap virtual address for"
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2004-06-10 06:45:38 -06:00
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" ring buffer\n");
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2004-08-27 03:14:30 -06:00
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return DRM_ERR(ENOMEM);
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2004-06-10 06:45:38 -06:00
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}
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2004-08-27 03:14:30 -06:00
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dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
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2004-06-10 06:45:38 -06:00
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dev_priv->back_offset = init->back_offset;
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dev_priv->front_offset = init->front_offset;
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dev_priv->current_page = 0;
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dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
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/* We are using separate values as placeholders for mechanisms for
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* private backbuffer/depthbuffer usage.
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*/
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dev_priv->use_mi_batchbuffer_start = 0;
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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dev_priv->allow_batchbuffer = 1;
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2004-08-27 03:14:30 -06:00
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/* Program Hardware Status Page */
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2004-07-29 05:09:22 -06:00
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#ifdef __FreeBSD__
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2004-08-27 03:14:30 -06:00
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dev_priv->hw_status_page =
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2004-09-27 14:14:31 -06:00
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contigmalloc(PAGE_SIZE, DRM(M_DRM), M_NOWAIT, 0ul, 0, 0, 0);
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2004-08-27 03:14:30 -06:00
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dev_priv->dma_status_page = vtophys(dev_priv->hw_status_page);
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2004-07-29 05:09:22 -06:00
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#else
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2004-08-27 03:14:30 -06:00
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dev_priv->hw_status_page =
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pci_alloc_consistent(dev->pdev, PAGE_SIZE,
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&dev_priv->dma_status_page);
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2004-07-29 05:09:22 -06:00
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#endif
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2004-06-10 06:45:38 -06:00
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2004-08-27 03:14:30 -06:00
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if (!dev_priv->hw_status_page) {
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2004-06-10 06:45:38 -06:00
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dev->dev_private = (void *)dev_priv;
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2004-07-29 05:09:22 -06:00
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i915_dma_cleanup(dev);
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2004-06-10 06:45:38 -06:00
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DRM_ERROR("Can not allocate hardware status page\n");
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return DRM_ERR(ENOMEM);
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}
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2004-08-27 03:14:30 -06:00
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memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
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2004-06-10 06:45:38 -06:00
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DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
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2004-08-27 03:14:30 -06:00
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I915_WRITE(0x02080, dev_priv->dma_status_page);
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2004-06-10 06:45:38 -06:00
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DRM_DEBUG("Enabled hardware status page\n");
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2004-08-27 03:14:30 -06:00
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2004-06-10 06:45:38 -06:00
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dev->dev_private = (void *)dev_priv;
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2004-08-27 03:14:30 -06:00
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return 0;
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2004-06-10 06:45:38 -06:00
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}
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2005-01-06 10:51:32 -07:00
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static int i915_dma_resume(drm_device_t * dev)
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2004-06-10 06:45:38 -06:00
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{
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2004-08-27 03:14:30 -06:00
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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2004-06-10 06:45:38 -06:00
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2004-08-27 03:14:30 -06:00
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DRM_DEBUG("%s\n", __FUNCTION__);
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if (!dev_priv->sarea) {
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2004-06-10 06:45:38 -06:00
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DRM_ERROR("can not find sarea!\n");
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return DRM_ERR(EINVAL);
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}
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2004-08-27 03:14:30 -06:00
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if (!dev_priv->mmio_map) {
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2004-06-10 06:45:38 -06:00
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DRM_ERROR("can not find mmio map!\n");
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return DRM_ERR(EINVAL);
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}
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2004-08-27 03:14:30 -06:00
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if (dev_priv->ring.map.handle == NULL) {
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DRM_ERROR("can not ioremap virtual address for"
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2004-06-10 06:45:38 -06:00
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" ring buffer\n");
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2004-08-27 03:14:30 -06:00
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return DRM_ERR(ENOMEM);
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2004-06-10 06:45:38 -06:00
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}
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2004-08-27 03:14:30 -06:00
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/* Program Hardware Status Page */
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if (!dev_priv->hw_status_page) {
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2004-06-10 06:45:38 -06:00
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DRM_ERROR("Can not find hardware status page\n");
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return DRM_ERR(EINVAL);
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}
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DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
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2004-08-27 03:14:30 -06:00
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I915_WRITE(0x02080, dev_priv->dma_status_page);
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2004-06-10 06:45:38 -06:00
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DRM_DEBUG("Enabled hardware status page\n");
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2004-08-27 03:14:30 -06:00
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return 0;
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2004-06-10 06:45:38 -06:00
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}
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2004-08-27 03:14:30 -06:00
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int i915_dma_init(DRM_IOCTL_ARGS)
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2004-06-10 06:45:38 -06:00
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{
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DRM_DEVICE;
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2004-08-27 03:14:30 -06:00
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drm_i915_private_t *dev_priv;
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drm_i915_init_t init;
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int retcode = 0;
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DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
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sizeof(init));
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switch (init.func) {
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case I915_INIT_DMA:
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2004-09-27 14:14:31 -06:00
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dev_priv = DRM(alloc) (sizeof(drm_i915_private_t),
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2004-08-27 03:14:30 -06:00
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DRM_MEM_DRIVER);
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if (dev_priv == NULL)
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return DRM_ERR(ENOMEM);
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retcode = i915_initialize(dev, dev_priv, &init);
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break;
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case I915_CLEANUP_DMA:
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retcode = i915_dma_cleanup(dev);
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break;
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case I915_RESUME_DMA:
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2005-01-06 10:51:32 -07:00
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retcode = i915_dma_resume(dev);
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2004-08-27 03:14:30 -06:00
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break;
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default:
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retcode = -EINVAL;
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break;
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}
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2004-06-10 06:45:38 -06:00
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2004-08-27 03:14:30 -06:00
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return retcode;
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}
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2004-06-10 06:45:38 -06:00
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/* Implement basically the same security restrictions as hardware does
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* for MI_BATCH_NON_SECURE. These can be made stricter at any time.
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|
|
*
|
|
|
|
* Most of the calculations below involve calculating the size of a
|
|
|
|
* particular instruction. It's important to get the size right as
|
|
|
|
* that tells us where the next instruction to check is. Any illegal
|
|
|
|
* instruction detected will be given a size of zero, which is a
|
|
|
|
* signal to abort the rest of the buffer.
|
|
|
|
*/
|
2004-08-27 03:14:30 -06:00
|
|
|
static int do_validate_cmd(int cmd)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
switch (((cmd >> 29) & 0x7)) {
|
2004-06-10 06:45:38 -06:00
|
|
|
case 0x0:
|
2004-08-27 03:14:30 -06:00
|
|
|
switch ((cmd >> 23) & 0x3f) {
|
|
|
|
case 0x0:
|
|
|
|
return 1; /* MI_NOOP */
|
|
|
|
case 0x4:
|
|
|
|
return 1; /* MI_FLUSH */
|
|
|
|
default:
|
|
|
|
return 0; /* disallow everything else */
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|
|
|
|
break;
|
2004-08-27 03:14:30 -06:00
|
|
|
case 0x1:
|
2004-06-10 06:45:38 -06:00
|
|
|
return 0; /* reserved */
|
2004-08-27 03:14:30 -06:00
|
|
|
case 0x2:
|
|
|
|
return (cmd & 0xff) + 2; /* 2d commands */
|
2004-06-10 06:45:38 -06:00
|
|
|
case 0x3:
|
2004-08-27 03:14:30 -06:00
|
|
|
if (((cmd >> 24) & 0x1f) <= 0x18)
|
2004-06-10 06:45:38 -06:00
|
|
|
return 1;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
switch ((cmd >> 24) & 0x1f) {
|
|
|
|
case 0x1c:
|
2004-06-10 06:45:38 -06:00
|
|
|
return 1;
|
|
|
|
case 0x1d:
|
2004-08-27 03:14:30 -06:00
|
|
|
switch ((cmd >> 16) & 0xff) {
|
|
|
|
case 0x3:
|
2004-07-23 10:12:27 -06:00
|
|
|
return (cmd & 0x1f) + 2;
|
2004-08-27 03:14:30 -06:00
|
|
|
case 0x4:
|
2004-07-23 10:12:27 -06:00
|
|
|
return (cmd & 0xf) + 2;
|
2004-08-27 03:14:30 -06:00
|
|
|
default:
|
2004-07-23 10:12:27 -06:00
|
|
|
return (cmd & 0xffff) + 2;
|
|
|
|
}
|
2004-08-27 03:14:30 -06:00
|
|
|
case 0x1e:
|
|
|
|
if (cmd & (1 << 23))
|
2004-06-10 06:45:38 -06:00
|
|
|
return (cmd & 0xffff) + 1;
|
|
|
|
else
|
|
|
|
return 1;
|
|
|
|
case 0x1f:
|
2004-08-27 03:14:30 -06:00
|
|
|
if ((cmd & (1 << 23)) == 0) /* inline vertices */
|
2004-06-10 06:45:38 -06:00
|
|
|
return (cmd & 0x1ffff) + 2;
|
2004-08-27 03:14:30 -06:00
|
|
|
else if (cmd & (1 << 17)) /* indirect random */
|
2004-06-10 06:45:38 -06:00
|
|
|
if ((cmd & 0xffff) == 0)
|
2004-08-27 03:14:30 -06:00
|
|
|
return 0; /* unknown length, too hard */
|
2004-06-10 06:45:38 -06:00
|
|
|
else
|
|
|
|
return (((cmd & 0xffff) + 1) / 2) + 1;
|
|
|
|
else
|
2004-08-27 03:14:30 -06:00
|
|
|
return 2; /* indirect sequential */
|
|
|
|
default:
|
2004-06-10 06:45:38 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
static int validate_cmd(int cmd)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
int ret = do_validate_cmd(cmd);
|
|
|
|
|
2004-06-10 06:45:38 -06:00
|
|
|
/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2004-06-10 06:45:38 -06:00
|
|
|
int i;
|
|
|
|
RING_LOCALS;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
for (i = 0; i < dwords;) {
|
2004-06-10 06:45:38 -06:00
|
|
|
int cmd, sz;
|
|
|
|
|
|
|
|
if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
|
2004-08-27 03:14:30 -06:00
|
|
|
return DRM_ERR(EINVAL);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
/* printk("%d/%d ", i, dwords); */
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
|
|
|
|
return DRM_ERR(EINVAL);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
BEGIN_LP_RING(sz);
|
2004-06-10 06:45:38 -06:00
|
|
|
OUT_RING(cmd);
|
|
|
|
|
|
|
|
while (++i, --sz) {
|
2004-08-27 03:14:30 -06:00
|
|
|
if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
|
|
|
|
sizeof(cmd))) {
|
|
|
|
return DRM_ERR(EINVAL);
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|
|
|
|
OUT_RING(cmd);
|
|
|
|
}
|
|
|
|
ADVANCE_LP_RING();
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
static int i915_emit_box(drm_device_t * dev,
|
|
|
|
drm_clip_rect_t __user * boxes,
|
|
|
|
int i, int DR1, int DR4)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_clip_rect_t box;
|
|
|
|
RING_LOCALS;
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
|
2004-06-10 06:45:38 -06:00
|
|
|
return EFAULT;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
|
2004-06-10 06:45:38 -06:00
|
|
|
DRM_ERROR("Bad box %d,%d..%d,%d\n",
|
|
|
|
box.x1, box.y1, box.x2, box.y2);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
BEGIN_LP_RING(6);
|
2004-08-27 03:14:30 -06:00
|
|
|
OUT_RING(GFX_OP_DRAWRECT_INFO);
|
|
|
|
OUT_RING(DR1);
|
|
|
|
OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
|
|
|
|
OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
|
|
|
|
OUT_RING(DR4);
|
|
|
|
OUT_RING(0);
|
2004-06-10 06:45:38 -06:00
|
|
|
ADVANCE_LP_RING();
|
2004-08-27 03:14:30 -06:00
|
|
|
|
2004-06-10 06:45:38 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
static int i915_dispatch_cmdbuffer(drm_device_t * dev,
|
|
|
|
drm_i915_cmdbuffer_t * cmd)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
int nbox = cmd->num_cliprects;
|
2004-06-10 06:45:38 -06:00
|
|
|
int i = 0, count, ret;
|
|
|
|
|
|
|
|
if (cmd->sz & 0x3) {
|
|
|
|
DRM_ERROR("alignment");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
2004-08-27 03:14:30 -06:00
|
|
|
|
|
|
|
i915_kernel_lost_context(dev);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
count = nbox ? nbox : 1;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
for (i = 0; i < count; i++) {
|
2004-06-10 06:45:38 -06:00
|
|
|
if (i < nbox) {
|
2004-08-27 03:14:30 -06:00
|
|
|
ret = i915_emit_box(dev, cmd->cliprects, i,
|
|
|
|
cmd->DR1, cmd->DR4);
|
|
|
|
if (ret)
|
2004-06-10 06:45:38 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
|
|
|
|
if (ret)
|
2004-06-10 06:45:38 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
static int i915_dispatch_batchbuffer(drm_device_t * dev,
|
|
|
|
drm_i915_batchbuffer_t * batch)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_clip_rect_t __user *boxes = batch->cliprects;
|
|
|
|
int nbox = batch->num_cliprects;
|
2004-06-10 06:45:38 -06:00
|
|
|
int i = 0, count;
|
2004-08-27 03:14:30 -06:00
|
|
|
RING_LOCALS;
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
if ((batch->start | batch->used) & 0x7) {
|
|
|
|
DRM_ERROR("alignment");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
2004-08-27 03:14:30 -06:00
|
|
|
|
|
|
|
i915_kernel_lost_context(dev);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
count = nbox ? nbox : 1;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
for (i = 0; i < count; i++) {
|
2004-06-10 06:45:38 -06:00
|
|
|
if (i < nbox) {
|
2004-08-27 03:14:30 -06:00
|
|
|
int ret = i915_emit_box(dev, boxes, i,
|
|
|
|
batch->DR1, batch->DR4);
|
|
|
|
if (ret)
|
2004-06-10 06:45:38 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_priv->use_mi_batchbuffer_start) {
|
|
|
|
BEGIN_LP_RING(2);
|
2004-08-27 03:14:30 -06:00
|
|
|
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
|
|
|
|
OUT_RING(batch->start | MI_BATCH_NON_SECURE);
|
2004-06-10 06:45:38 -06:00
|
|
|
ADVANCE_LP_RING();
|
2004-08-27 03:14:30 -06:00
|
|
|
} else {
|
2004-06-10 06:45:38 -06:00
|
|
|
BEGIN_LP_RING(4);
|
2004-08-27 03:14:30 -06:00
|
|
|
OUT_RING(MI_BATCH_BUFFER);
|
|
|
|
OUT_RING(batch->start | MI_BATCH_NON_SECURE);
|
|
|
|
OUT_RING(batch->start + batch->used - 4);
|
|
|
|
OUT_RING(0);
|
2004-06-10 06:45:38 -06:00
|
|
|
ADVANCE_LP_RING();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
|
|
|
|
|
|
|
|
BEGIN_LP_RING(4);
|
2004-08-27 03:14:30 -06:00
|
|
|
OUT_RING(CMD_STORE_DWORD_IDX);
|
|
|
|
OUT_RING(20);
|
|
|
|
OUT_RING(dev_priv->counter);
|
|
|
|
OUT_RING(0);
|
2004-06-10 06:45:38 -06:00
|
|
|
ADVANCE_LP_RING();
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
static int i915_dispatch_flip(drm_device_t * dev)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2004-06-10 06:45:38 -06:00
|
|
|
RING_LOCALS;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
|
|
|
|
__FUNCTION__,
|
|
|
|
dev_priv->current_page,
|
|
|
|
dev_priv->sarea_priv->pf_current_page);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
i915_kernel_lost_context(dev);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
BEGIN_LP_RING(2);
|
|
|
|
OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
|
|
|
|
OUT_RING(0);
|
2004-06-10 06:45:38 -06:00
|
|
|
ADVANCE_LP_RING();
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
BEGIN_LP_RING(6);
|
|
|
|
OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
|
|
|
|
OUT_RING(0);
|
|
|
|
if (dev_priv->current_page == 0) {
|
|
|
|
OUT_RING(dev_priv->back_offset);
|
2004-06-10 06:45:38 -06:00
|
|
|
dev_priv->current_page = 1;
|
|
|
|
} else {
|
2004-08-27 03:14:30 -06:00
|
|
|
OUT_RING(dev_priv->front_offset);
|
2004-06-10 06:45:38 -06:00
|
|
|
dev_priv->current_page = 0;
|
|
|
|
}
|
|
|
|
OUT_RING(0);
|
|
|
|
ADVANCE_LP_RING();
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
BEGIN_LP_RING(2);
|
|
|
|
OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
|
|
|
|
OUT_RING(0);
|
2004-06-10 06:45:38 -06:00
|
|
|
ADVANCE_LP_RING();
|
|
|
|
|
|
|
|
dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
|
|
|
|
|
|
|
|
BEGIN_LP_RING(4);
|
2004-08-27 03:14:30 -06:00
|
|
|
OUT_RING(CMD_STORE_DWORD_IDX);
|
|
|
|
OUT_RING(20);
|
|
|
|
OUT_RING(dev_priv->counter);
|
|
|
|
OUT_RING(0);
|
2004-06-10 06:45:38 -06:00
|
|
|
ADVANCE_LP_RING();
|
|
|
|
|
|
|
|
dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
static int i915_quiescent(drm_device_t * dev)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
i915_kernel_lost_context(dev);
|
|
|
|
return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
int i915_flush_ioctl(DRM_IOCTL_ARGS)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
|
2004-06-10 06:45:38 -06:00
|
|
|
DRM_ERROR("i915_flush_ioctl called without lock held\n");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
return i915_quiescent(dev);
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
int i915_batchbuffer(DRM_IOCTL_ARGS)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
2004-08-27 03:14:30 -06:00
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
u32 *hw_status = dev_priv->hw_status_page;
|
|
|
|
drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
|
|
|
|
dev_priv->sarea_priv;
|
2004-06-10 06:45:38 -06:00
|
|
|
drm_i915_batchbuffer_t batch;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!dev_priv->allow_batchbuffer) {
|
|
|
|
DRM_ERROR("Batchbuffer ioctl disabled\n");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
|
|
|
|
sizeof(batch));
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
|
|
|
|
batch.start, batch.used, batch.num_cliprects);
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
|
2004-06-10 06:45:38 -06:00
|
|
|
DRM_ERROR("i915_batchbuffer called without lock held\n");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
|
2004-06-10 06:45:38 -06:00
|
|
|
batch.num_cliprects *
|
|
|
|
sizeof(drm_clip_rect_t)))
|
|
|
|
return DRM_ERR(EFAULT);
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
ret = i915_dispatch_batchbuffer(dev, &batch);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
sarea_priv->last_dispatch = (int)hw_status[5];
|
2004-06-10 06:45:38 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
int i915_cmdbuffer(DRM_IOCTL_ARGS)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
2004-08-27 03:14:30 -06:00
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
u32 *hw_status = dev_priv->hw_status_page;
|
|
|
|
drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
|
|
|
|
dev_priv->sarea_priv;
|
2004-06-10 06:45:38 -06:00
|
|
|
drm_i915_cmdbuffer_t cmdbuf;
|
|
|
|
int ret;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
|
|
|
|
sizeof(cmdbuf));
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
|
|
|
|
cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
|
2004-06-10 06:45:38 -06:00
|
|
|
DRM_ERROR("i915_cmdbuffer called without lock held\n");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (cmdbuf.num_cliprects &&
|
|
|
|
DRM_VERIFYAREA_READ(cmdbuf.cliprects,
|
2004-06-10 06:45:38 -06:00
|
|
|
cmdbuf.num_cliprects *
|
|
|
|
sizeof(drm_clip_rect_t))) {
|
|
|
|
DRM_ERROR("Fault accessing cliprects\n");
|
|
|
|
return DRM_ERR(EFAULT);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
|
2004-06-10 06:45:38 -06:00
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
sarea_priv->last_dispatch = (int)hw_status[5];
|
2004-06-10 06:45:38 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
int i915_do_cleanup_pageflip(drm_device_t * dev)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
DRM_DEBUG("%s\n", __FUNCTION__);
|
|
|
|
if (dev_priv->current_page != 0)
|
2004-08-27 03:14:30 -06:00
|
|
|
i915_dispatch_flip(dev);
|
2004-06-10 06:45:38 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
int i915_flip_bufs(DRM_IOCTL_ARGS)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
|
|
|
|
DRM_DEBUG("%s\n", __FUNCTION__);
|
2004-08-27 03:14:30 -06:00
|
|
|
if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
|
2004-06-10 06:45:38 -06:00
|
|
|
DRM_ERROR("i915_flip_buf called without lock held\n");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
return i915_dispatch_flip(dev);
|
2004-06-10 06:45:38 -06:00
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
int i915_getparam(DRM_IOCTL_ARGS)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_i915_getparam_t param;
|
|
|
|
int value;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (!dev_priv) {
|
|
|
|
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
2004-06-10 06:45:38 -06:00
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
|
2004-06-10 06:45:38 -06:00
|
|
|
sizeof(param));
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
switch (param.param) {
|
2004-06-10 06:45:38 -06:00
|
|
|
case I915_PARAM_IRQ_ACTIVE:
|
|
|
|
value = dev->irq ? 1 : 0;
|
|
|
|
break;
|
|
|
|
case I915_PARAM_ALLOW_BATCHBUFFER:
|
|
|
|
value = dev_priv->allow_batchbuffer ? 1 : 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DRM_ERROR("Unkown parameter %d\n", param.param);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
|
2004-06-10 06:45:38 -06:00
|
|
|
DRM_ERROR("DRM_COPY_TO_USER failed\n");
|
|
|
|
return DRM_ERR(EFAULT);
|
|
|
|
}
|
2004-08-27 03:14:30 -06:00
|
|
|
|
2004-06-10 06:45:38 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
int i915_setparam(DRM_IOCTL_ARGS)
|
2004-06-10 06:45:38 -06:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_i915_setparam_t param;
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
if (!dev_priv) {
|
|
|
|
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
2004-06-10 06:45:38 -06:00
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
|
|
|
|
sizeof(param));
|
2004-06-10 06:45:38 -06:00
|
|
|
|
2004-08-27 03:14:30 -06:00
|
|
|
switch (param.param) {
|
2004-06-10 06:45:38 -06:00
|
|
|
case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
|
|
|
|
dev_priv->use_mi_batchbuffer_start = param.value;
|
|
|
|
break;
|
|
|
|
case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
|
|
|
|
dev_priv->tex_lru_log_granularity = param.value;
|
|
|
|
break;
|
|
|
|
case I915_SETPARAM_ALLOW_BATCHBUFFER:
|
|
|
|
dev_priv->allow_batchbuffer = param.value;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DRM_ERROR("unknown parameter %d\n", param.param);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2004-08-17 07:10:05 -06:00
|
|
|
|
2004-09-27 14:14:31 -06:00
|
|
|
static void i915_driver_pretakedown(drm_device_t *dev)
|
2004-08-17 07:10:05 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
if (dev->dev_private) {
|
2004-08-17 07:10:05 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2004-08-27 03:14:30 -06:00
|
|
|
i915_mem_takedown(&(dev_priv->agp_heap));
|
|
|
|
}
|
|
|
|
i915_dma_cleanup(dev);
|
2004-08-17 07:10:05 -06:00
|
|
|
}
|
|
|
|
|
2004-09-27 14:14:31 -06:00
|
|
|
static void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp)
|
2004-08-17 07:10:05 -06:00
|
|
|
{
|
2004-08-27 03:14:30 -06:00
|
|
|
if (dev->dev_private) {
|
2004-08-17 07:10:05 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2004-08-27 03:14:30 -06:00
|
|
|
i915_mem_release(dev, filp, dev_priv->agp_heap);
|
2004-08-17 07:10:05 -06:00
|
|
|
}
|
|
|
|
}
|
2004-09-27 14:14:31 -06:00
|
|
|
|
|
|
|
void i915_driver_register_fns(drm_device_t *dev)
|
|
|
|
{
|
|
|
|
dev->driver_features =
|
|
|
|
DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR |
|
|
|
|
DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED;
|
|
|
|
dev->fn_tbl.pretakedown = i915_driver_pretakedown;
|
|
|
|
dev->fn_tbl.prerelease = i915_driver_prerelease;
|
|
|
|
dev->fn_tbl.irq_preinstall = i915_driver_irq_preinstall;
|
|
|
|
dev->fn_tbl.irq_postinstall = i915_driver_irq_postinstall;
|
|
|
|
dev->fn_tbl.irq_uninstall = i915_driver_irq_uninstall;
|
|
|
|
dev->fn_tbl.irq_handler = i915_driver_irq_handler;
|
|
|
|
|
|
|
|
dev->counters += 4;
|
|
|
|
dev->types[6] = _DRM_STAT_IRQ;
|
|
|
|
dev->types[7] = _DRM_STAT_PRIMARY;
|
|
|
|
dev->types[8] = _DRM_STAT_SECONDARY;
|
|
|
|
dev->types[9] = _DRM_STAT_DMA;
|
|
|
|
}
|