2007-04-11 12:47:58 -06:00
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/*
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* Copyright (c) 2007 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
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* 2004 Sylvain Meyer
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*
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* GPL/BSD dual license
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*/
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2007-04-10 11:31:10 -06:00
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#include "drmP.h"
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#include "drm.h"
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#include "drm_sarea.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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2007-04-11 12:47:58 -06:00
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/**
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* i915_probe_agp - get AGP bootup configuration
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* @pdev: PCI device
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* @aperture_size: returns AGP aperture configured size
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* @preallocated_size: returns size of BIOS preallocated AGP space
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*
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* Since Intel integrated graphics are UMA, the BIOS has to set aside
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* some RAM for the framebuffer at early boot. This code figures out
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* how much was set aside so we can use it for our own purposes.
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*/
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int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
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unsigned long *preallocated_size)
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{
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struct pci_dev *bridge_dev;
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u16 tmp = 0;
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unsigned long overhead;
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bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
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if (!bridge_dev) {
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DRM_ERROR("bridge device not found\n");
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return -1;
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}
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/* Get the fb aperture size and "stolen" memory amount. */
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pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
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pci_dev_put(bridge_dev);
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*aperture_size = 1024 * 1024;
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*preallocated_size = 1024 * 1024;
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switch (pdev->device) {
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2007-04-11 13:52:57 -06:00
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case PCI_DEVICE_ID_INTEL_82830_CGC:
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case PCI_DEVICE_ID_INTEL_82845G_HB:
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case PCI_DEVICE_ID_INTEL_82855GM_IG:
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case PCI_DEVICE_ID_INTEL_82865_IG:
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2007-04-11 12:47:58 -06:00
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if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
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*aperture_size *= 64;
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else
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*aperture_size *= 128;
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break;
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2007-04-11 13:52:57 -06:00
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default:
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/* 9xx supports large sizes, just look at the length */
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*aperture_size = pci_resource_len(pdev, 2);
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break;
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2007-04-11 12:47:58 -06:00
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}
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/*
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* Some of the preallocated space is taken by the GTT
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* and popup. GTT is 1K per MB of aperture size, and popup is 4K.
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*/
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overhead = (*aperture_size / 1024) + 4096;
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switch (tmp & INTEL_855_GMCH_GMS_MASK) {
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case INTEL_855_GMCH_GMS_STOLEN_1M:
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break; /* 1M already */
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case INTEL_855_GMCH_GMS_STOLEN_4M:
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*preallocated_size *= 4;
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break;
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case INTEL_855_GMCH_GMS_STOLEN_8M:
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*preallocated_size *= 8;
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break;
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case INTEL_855_GMCH_GMS_STOLEN_16M:
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*preallocated_size *= 16;
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break;
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case INTEL_855_GMCH_GMS_STOLEN_32M:
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*preallocated_size *= 32;
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break;
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case INTEL_915G_GMCH_GMS_STOLEN_48M:
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*preallocated_size *= 48;
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break;
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case INTEL_915G_GMCH_GMS_STOLEN_64M:
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*preallocated_size *= 64;
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break;
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case INTEL_855_GMCH_GMS_DISABLED:
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DRM_ERROR("video memory is disabled\n");
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return -1;
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default:
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DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
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tmp & INTEL_855_GMCH_GMS_MASK);
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return -1;
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}
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*preallocated_size -= overhead;
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return 0;
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}
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2007-04-11 08:07:54 -06:00
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/**
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* i915_driver_load - setup chip and create an initial config
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* @dev: DRM device
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* @flags: startup flags
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*
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* The driver load routine has to do several things:
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* - drive output discovery via intel_modeset_init()
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* - initialize the memory manager
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* - allocate initial config memory
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* - setup the DRM framebuffer with the allocated memory
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*/
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2007-04-10 11:31:10 -06:00
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int i915_driver_load(drm_device_t *dev, unsigned long flags)
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{
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drm_i915_private_t *dev_priv;
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drm_i915_init_t init;
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2007-04-11 08:07:54 -06:00
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drm_buffer_object_t *entry;
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2007-04-12 10:01:53 -06:00
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drm_local_map_t *map;
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2007-04-11 08:07:54 -06:00
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struct drm_framebuffer *fb;
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2007-04-11 12:47:58 -06:00
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unsigned long agp_size, prealloc_size;
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2007-04-12 10:01:53 -06:00
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unsigned long sareapage;
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2007-04-11 12:47:58 -06:00
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int hsize, vsize, bytes_per_pixel, size, ret;
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2007-04-10 11:31:10 -06:00
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dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
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if (dev_priv == NULL)
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return DRM_ERR(ENOMEM);
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memset(dev_priv, 0, sizeof(drm_i915_private_t));
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dev->dev_private = (void *)dev_priv;
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// dev_priv->flags = flags;
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/* i915 has 4 more counters */
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dev->counters += 4;
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dev->types[6] = _DRM_STAT_IRQ;
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dev->types[7] = _DRM_STAT_PRIMARY;
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dev->types[8] = _DRM_STAT_SECONDARY;
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dev->types[9] = _DRM_STAT_DMA;
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if (IS_I9XX(dev)) {
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dev_priv->mmiobase = drm_get_resource_start(dev, 0);
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dev_priv->mmiolen = drm_get_resource_len(dev, 0);
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2007-04-11 12:47:58 -06:00
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dev->mode_config.fb_base = dev_priv->baseaddr =
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drm_get_resource_start(dev, 2) & 0xff000000;
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2007-04-10 11:31:10 -06:00
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} else if (drm_get_resource_start(dev, 1)) {
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dev_priv->mmiobase = drm_get_resource_start(dev, 1);
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dev_priv->mmiolen = drm_get_resource_len(dev, 1);
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2007-04-11 12:47:58 -06:00
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dev->mode_config.fb_base = dev_priv->baseaddr =
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drm_get_resource_start(dev, 0) & 0xff000000;
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2007-04-10 11:31:10 -06:00
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} else {
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DRM_ERROR("Unable to find MMIO registers\n");
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return -ENODEV;
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}
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ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
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_DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio_map);
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if (ret != 0) {
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DRM_ERROR("Cannot add mapping for MMIO registers\n");
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return ret;
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}
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2007-04-12 10:01:53 -06:00
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/* prebuild the SAREA */
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sareapage = max(SAREA_MAX, PAGE_SIZE);
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ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
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&map);
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2007-04-10 11:31:10 -06:00
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if (ret) {
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2007-04-12 10:01:53 -06:00
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DRM_ERROR("SAREA setup failed\n");
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2007-04-10 11:31:10 -06:00
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return ret;
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}
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DRM_GETSAREA();
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if (!dev_priv->sarea) {
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DRM_ERROR("can not find sarea!\n");
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dev->dev_private = (void *)dev_priv;
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i915_dma_cleanup(dev);
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return DRM_ERR(EINVAL);
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}
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2007-04-11 08:07:54 -06:00
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/* FIXME: assume sarea_priv is right after SAREA */
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dev_priv->sarea_priv = dev_priv->sarea->handle + sizeof(drm_sarea_t);
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2007-04-10 11:31:10 -06:00
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2007-04-11 08:07:54 -06:00
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/*
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* Initialize the memory manager for local and AGP space
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*/
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2007-04-10 11:31:10 -06:00
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drm_bo_driver_init(dev);
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2007-04-11 12:47:58 -06:00
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i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
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drm_bo_init_mm(dev, DRM_BO_MEM_PRIV0, dev_priv->baseaddr,
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prealloc_size);
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2007-04-11 08:07:54 -06:00
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/* Allocate scanout buffer and command ring */
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/* FIXME: types and other args correct? */
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2007-04-11 12:47:58 -06:00
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hsize = 1280;
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vsize = 800;
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bytes_per_pixel = 4;
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size = hsize * vsize * bytes_per_pixel;
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2007-04-11 13:52:57 -06:00
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drm_buffer_object_create(dev, size, drm_bo_type_kernel,
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2007-04-11 08:07:54 -06:00
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DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
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DRM_BO_FLAG_MEM_PRIV0 | DRM_BO_FLAG_NO_MOVE,
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0, PAGE_SIZE, 0,
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&entry);
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2007-04-10 11:31:10 -06:00
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intel_modeset_init(dev);
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2007-04-11 08:07:54 -06:00
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fb = drm_framebuffer_create(dev);
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if (!fb) {
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DRM_ERROR("failed to allocate fb\n");
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return -EINVAL;
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}
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2007-04-11 12:47:58 -06:00
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fb->width = hsize;
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fb->height = vsize;
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fb->pitch = hsize;
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fb->bits_per_pixel = bytes_per_pixel * 8;
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fb->depth = bytes_per_pixel * 8;
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2007-04-11 08:07:54 -06:00
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fb->offset = entry->offset;
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fb->bo = entry;
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drm_initial_config(dev, fb, false);
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drmfb_probe(dev, fb);
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2007-04-10 22:43:02 -06:00
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#if 0
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2007-04-10 11:31:10 -06:00
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/* FIXME: command ring needs AGP space, do we own it at this point? */
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2007-04-10 22:04:18 -06:00
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dev_priv->ring.Start = dev_priv->baseaddr;
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2007-04-10 11:31:10 -06:00
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dev_priv->ring.End = 128*1024;
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dev_priv->ring.Size = 128*1024;
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dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
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dev_priv->ring.map.offset = dev_priv->ring.Start;
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dev_priv->ring.map.size = dev_priv->ring.Size;
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dev_priv->ring.map.type = 0;
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dev_priv->ring.map.flags = 0;
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dev_priv->ring.map.mtrr = 0;
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drm_core_ioremap(&dev_priv->ring.map, dev);
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if (dev_priv->ring.map.handle == NULL) {
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dev->dev_private = (void *)dev_priv;
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i915_dma_cleanup(dev);
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DRM_ERROR("can not ioremap virtual address for"
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" ring buffer\n");
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return DRM_ERR(ENOMEM);
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}
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dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
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dev_priv->cpp = 4;
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dev_priv->sarea_priv->pf_current_page = 0;
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/* We are using separate values as placeholders for mechanisms for
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* private backbuffer/depthbuffer usage.
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*/
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dev_priv->use_mi_batchbuffer_start = 0;
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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dev_priv->allow_batchbuffer = 1;
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/* Program Hardware Status Page */
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dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
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0xffffffff);
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if (!dev_priv->status_page_dmah) {
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dev->dev_private = (void *)dev_priv;
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i915_dma_cleanup(dev);
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DRM_ERROR("Can not allocate hardware status page\n");
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return DRM_ERR(ENOMEM);
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}
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dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
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dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
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memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
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DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
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I915_WRITE(0x02080, dev_priv->dma_status_page);
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DRM_DEBUG("Enabled hardware status page\n");
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2007-04-10 22:43:02 -06:00
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#endif
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2007-04-10 11:31:10 -06:00
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return 0;
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}
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int i915_driver_unload(drm_device_t *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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2007-04-11 08:07:54 -06:00
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struct drm_framebuffer *fb;
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2007-04-10 11:31:10 -06:00
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2007-04-11 08:07:54 -06:00
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/* FIXME: remove framebuffer */
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2007-04-11 08:21:24 -06:00
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intel_modeset_cleanup(dev);
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2007-04-10 11:31:10 -06:00
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drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
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dev->dev_private = NULL;
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return 0;
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}
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void i915_driver_lastclose(drm_device_t * dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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i915_mem_takedown(&(dev_priv->agp_heap));
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i915_dma_cleanup(dev);
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dev_priv->mmio_map = NULL;
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}
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void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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i915_mem_release(dev, filp, dev_priv->agp_heap);
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}
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