386 lines
14 KiB
C
386 lines
14 KiB
C
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/*
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* Copyright 2006-2007 Advanced Micro Devices, Inc.
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* Copyright 2007 Jérôme Glisse
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Authors:
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* Jérôme Glisse <glisse@freedesktop.org>
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*/
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#ifndef __RADEON_MS_COMBIOS_H__
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#define __RADEON_MS_COMBIOS_H__
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#pragma pack(1)
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#define ROM_HEADER 0x48
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struct combios_header
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{
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uint8_t ucTypeDefinition;
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uint8_t ucExtFunctionCode;
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uint8_t ucOemID1;
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uint8_t ucOemID2;
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uint8_t ucBiosMajorRev;
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uint8_t ucBiosMinorRev;
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uint16_t usStructureSize;
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uint16_t usPointerToSmi;
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uint16_t usPointerToPmid;
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uint16_t usPointerToInitTable;
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uint16_t usPointerToCrcChecksumBlock;
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uint16_t usPointerToConfigFilename;
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uint16_t usPointerToLogonMessage;
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uint16_t usPointerToMiscInfo;
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uint16_t usPciBusDevInitCode;
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uint16_t usBiosRuntimeSegmentAddress;
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uint16_t usIoBaseAddress;
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uint16_t usSubsystemVendorID;
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uint16_t usSubsystemID;
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uint16_t usPostVendorID;
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uint16_t usInt10Offset;
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uint16_t usInt10Segment;
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uint16_t usMonitorInfo;
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uint16_t usPointerToConfigBlock;
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uint16_t usPointerToDacDelayInfo;
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uint16_t usPointerToCapDataStruct;
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uint16_t usPointerToInternalCrtTables;
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uint16_t usPointerToPllInfoBlock;
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uint16_t usPointerToTVInfoTable;
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uint16_t usPointerToDFPInfoTable;
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uint16_t usPointerToHWConfigTable;
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uint16_t usPointerToMMConfigTable;
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uint32_t ulTVStdPatchTableSignature;
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uint16_t usPointerToTVStdPatchTable;
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uint16_t usPointerToPanelInfoTable;
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uint16_t usPointerToAsicInfoTable;
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uint16_t usPointerToAuroraInfoTable;
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uint16_t usPointerToPllInitTable;
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uint16_t usPointerToMemoryConfigTable;
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uint16_t usPointerToSaveMaskTable;
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uint16_t usPointerHardCodedEdid;
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uint16_t usPointerToExtendedInitTable1;
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uint16_t usPointerToExtendedInitTable2;
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uint16_t usPointerToDynamicClkTable;
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uint16_t usPointerToReservedMemoryTable;
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uint16_t usPointerToBridgetInitTable;
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uint16_t usPointerToExtTMDSInitTable;
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uint16_t usPointerToMemClkInfoTable;
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uint16_t usPointerToExtDACTable;
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uint16_t usPointerToMiscInfoTable;
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};
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struct combios_pll_block
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{
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/* Usually 6 */
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uint8_t ucPLLBiosVersion;
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/* Size in bytes */
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uint8_t ucStructureSize;
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/* Dot clock entry used for accelerated modes */
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uint8_t ucDotClockEntry;
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/* Dot clock entry used for extended VGA modes */
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uint8_t ucDotClockEntryVga;
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/* Offset into internal clock table used for by VGA parameter table */
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uint16_t usPointerToInternalClock;
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/* Offset into actual programmed frequency table at POST */
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uint16_t usPointerToFreqTable;
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/* XCLK setting, (memory clock in 10 KHz units) */
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uint16_t usXclkSetting;
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/* MCLK setting, (engine clock in 10 KHz units) */
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uint16_t usMclkSetting;
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/* Number of PLL information block to follow, currently value is 3 */
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uint8_t ucPllInfoBlockNumber;
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/* Size of each PLL information block */
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uint8_t ucPllInfoBlockSize;
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/* Reference frequency of the dot clock */
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uint16_t usDotClockRefFreq;
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/* Reference Divider of the dot clock */
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uint16_t usDotClockRefDiv;
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/* Min Frequency supported before post divider for the dot clock */
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uint32_t ulDotClockMinFreq;
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/* Max Frequency can be supported for the dot clock */
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uint32_t ulDotClockMaxFreq;
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/* Reference frequency of the MCLK, engine clock */
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uint16_t usMclkRefFreq;
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/* Reference Divider of the MCLK, engine clock */
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uint16_t usMclkRefDiv;
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/* Min Frequency supported before post divider for MCLK, engine clock */
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uint32_t ulMclkMinFreq;
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/* Max Frequency can be supported for the MCLK, engine clock */
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uint32_t ulMclkMaxFreq;
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/* Reference frequency of the XCLK, memory clock */
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uint16_t usXclkRefFreq;
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/* Reference Divider of the XCLK, memory clock */
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uint16_t usXclkRefDiv;
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/* Min Frequency supported before post divider for XCLK, memory clock */
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uint32_t ulXclkMinFreq;
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/* Max Frequency can be supported for the XCLK, memory clock */
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uint32_t ulXclkMaxFreq;
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/*this is the PLL Information Table Extended structure version 10 */
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uint8_t ucNumberOfExtendedPllBlocks;
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uint8_t ucSizePLLDefinition;
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uint16_t ulCrystalFrequencyPixelClock_pll;
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uint32_t ulMinInputPixelClockPLLFrequency;
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uint32_t ulMaxInputPixelClockPLLFrequency;
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uint32_t ulMinOutputPixelClockPLLFrequency;
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uint32_t ulMaxOutputPixelClockPLLFrequency;
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/*version 11 */
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uint16_t ulCrystalFrequencyEngineClock_pll;
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uint32_t ulMinInputFrequencyEngineClock_pll;
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uint32_t ulMaxInputFrequencyEngineClock_pll;
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uint32_t ulMinOutputFrequencyEngineClock_pll;
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uint32_t ulMaxOutputFrequencyEngineClock_pll;
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uint16_t ulCrystalFrequencyMemoryClock_pll;
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uint32_t ulMinInputFrequencyMemoryClock_pll;
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uint32_t ulMaxInputFrequencyMemoryClock_pll;
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uint32_t ulMinOutputFrequencyMemoryClock_pll;
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uint32_t ulMaxOutputFrequencyMemoryClock_pll;
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uint32_t ulMaximumDACOutputFrequency;
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};
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#define MAX_NO_OF_LCD_RES_TIMING 25
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struct panel_information_table
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{
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uint8_t ucPanelIdentification;
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uint8_t ucPanelIDString[24];
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uint16_t usHorizontalSize;
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uint16_t usVerticalSize;
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uint16_t usFlatPanelType;
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uint8_t ucRedBitsPerPrimary;
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uint8_t ucGreenBitsPerPrimary;
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uint8_t ucBlueBitsPerPrimary;
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uint8_t ucReservedBitsPerPrimary;
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uint8_t ucPanelCaps;
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uint8_t ucPowerSequenceDelayStepsInMS;
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uint8_t ucSupportedRefreshRateExtended;
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uint16_t usExtendedPanelInfoTable;
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uint16_t usPtrToHalfFrameBufferInformationTable;
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uint16_t usVccOntoBlOn;
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uint16_t usOffDelay;
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uint16_t usRefDiv;
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uint8_t ucPostDiv;
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uint16_t usFeedBackDiv;
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uint8_t ucSpreadSpectrumType;
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uint16_t usSpreadSpectrumPercentage;
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uint8_t ucBackLightLevel;
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uint8_t ucBiasLevel;
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uint8_t ucPowerSequenceDelay;
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uint32_t ulPanelData;
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uint8_t ucPanelRefreshRateData;
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uint16_t usSupportedRefreshRate;
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uint16_t usModeTableOffset[MAX_NO_OF_LCD_RES_TIMING];
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};
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struct extended_panel_info_table
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{
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uint8_t ucExtendedPanelInfoTableVer;
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uint8_t ucSSDelay;
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uint8_t ucSSStepSizeIndex;
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};
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struct lcd_mode_table_center
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{
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uint16_t usHorizontalRes;
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uint16_t usVerticalRes;
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uint8_t ucModeType;
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uint16_t usOffset2ExpParamTable;
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uint16_t usOffset2TvParamTable;
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uint16_t usPixelClock;
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uint16_t usPixelClockAdjustment;
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uint16_t usFpPos;
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uint8_t ucReserved;
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uint8_t ucMiscBits;
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uint16_t usCrtcHTotal;
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uint16_t usCrtcHDisp;
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uint16_t usCrtcHSyncStrt;
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uint8_t ucCrtcHSyncWid;
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uint16_t usCrtcVTotal;
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uint16_t usCrtcVDisp;
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uint16_t usCrtcVSyncStrt;
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uint8_t ucOvrWidTop;
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};
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struct lcd_mode_table_exp
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{
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uint16_t usPixelClock;
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uint16_t usPixelClockAdjustment;
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uint16_t usFpPos;
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uint8_t ucReserved;
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uint8_t ucMiscBits;
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uint16_t usCrtcHTotal;
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uint16_t usCrtcHDisp;
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uint16_t usCrtcHSyncStrt;
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uint8_t ucCrtcHSyncWid;
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uint16_t usCrtcVTotal;
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uint16_t usCrtcVDisp;
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uint16_t usCrtcVSyncStrt;
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uint8_t ucOvrWidTop;
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uint16_t usHorizontalBlendRatio;
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uint32_t ulVgaVertStretching;
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uint16_t usCopVertStretching;
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uint16_t usVgaExtVertStretching;
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};
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struct tmds_pll_cntl_block
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{
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uint16_t usClockUpperRange;
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uint32_t ulPllSetting;
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};
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#define MAX_PLL_CNTL_ENTRIES 8
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struct combios_dfp_info_table
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{
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uint8_t ucDFPInfoTableRev;
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uint8_t ucDFPInfoTableSize;
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uint16_t usOffsetDetailedTimingTable;
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uint8_t ucReserved;
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uint8_t ucNumberOfClockRanges;
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uint16_t usMaxPixelClock;
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uint32_t ulInitValueTmdsPllCntl;
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uint32_t ulFinalValueTmdsPllCntl;
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struct tmds_pll_cntl_block sTmdsPllCntlBlock[MAX_PLL_CNTL_ENTRIES];
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};
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struct combios_exttmds_table_header
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{
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uint8_t ucTableRev;
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uint16_t usTableSize;
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uint8_t ucNoBlocks;
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};
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struct combios_exttmds_block_header
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{
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uint16_t usMaxFreq;
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uint8_t ucI2CSlaveAddr;
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uint8_t ucI2CLine;
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uint8_t ucConnectorId;
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uint8_t ucFlags;
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};
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/* Connector table - applicable from Piglet and later ASICs
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byte 0 (embedded revision)
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[7:4] = number of chips (valid number 1 - 15)
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[3:0] = revision number of table (valid number 1 - 15)
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byte 1 (Chip info)
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[7:4] = chip number, max. 15 (valid number 1 - 15)
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[3:0] = number of connectors for that chip, (valid number 1 - 15)
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(number of connectors = number of 'Connector info' entries
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for that chip)
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byte 2,3 (Connector info)
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[15:12] - connector type
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= 0 - no connector
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= 1 - proprietary
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= 2 - CRT
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= 3 - DVI-I
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= 4 - DVI-D
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= 5-15 - reserved for future expansion
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[11:8] - DDC line pair used for that connector
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= 0 - no DDC
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= 1 - MONID 0/1
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= 2 - DVI_DDC
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= 3 - VGA_DDC
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= 4 - CRT2_DDC
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= 5-15 - reserved for future expansion
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[5] - bit indicating presence of multiplexer for TV,CRT2
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[7:6] - reserved for future expansion
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[4] - TMDS type
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= 0 - internal TMDS
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= 1 - external TMDS
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[3:1] - reserved for future expansion
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[0] - DAC associated with that connector
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= 0 - CRT DAC
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= 1 - non-CRT DAC (e.g. TV DAC, external DAC ..)
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byte 4,5,6... - byte 4,5 can be another "Connector info" word
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describing another connector
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- or byte 5 is a "Chip info" byte for anther chip,
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then start with byte 5,6 to describe connectors
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for that chip
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- or byte 5 = 0 if all connectors for all chips on
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board have been described, no more connector left
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to describe.
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*/
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#define BIOS_CONNECTOR_INFO__TYPE__MASK 0xF000
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#define BIOS_CONNECTOR_INFO__TYPE__SHIFT 0x0000000C
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#define BIOS_CONNECTOR_TYPE__NONE 0x00000000
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#define BIOS_CONNECTOR_TYPE__PROPRIETARY 0x00000001
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#define BIOS_CONNECTOR_TYPE__CRT 0x00000002
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#define BIOS_CONNECTOR_TYPE__DVI_I 0x00000003
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#define BIOS_CONNECTOR_TYPE__DVI_D 0x00000004
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#define BIOS_CONNECTOR_INFO__DDC_LINE__MASK 0x0F00
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#define BIOS_CONNECTOR_INFO__DDC_LINE__SHIFT 0x00000008
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#define BIOS_DDC_LINE__NONE 0x00000000
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#define BIOS_DDC_LINE__MONID01 0x00000001
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#define BIOS_DDC_LINE__DVI 0x00000002
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#define BIOS_DDC_LINE__VGA 0x00000003
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#define BIOS_DDC_LINE__CRT2 0x00000004
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#define BIOS_DDC_LINE__GPIOPAD 0x00000005
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#define BIOS_DDC_LINE__ZV_LCDPAD 0x00000006
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#define BIOS_CONNECTOR_INFO__TMDS_TYPE__MASK 0x0010
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#define BIOS_CONNECTOR_INFO__TMDS_TYPE__SHIFT 0x00000004
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#define BIOS_TMDS_TYPE__INTERNAL 0x00000000
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#define BIOS_TMDS_TYPE__EXTERNAL 0x00000001
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#define BIOS_CONNECTOR_INFO__DAC_TYPE__MASK 0x0001
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#define BIOS_CONNECTOR_INFO__DAC_TYPE__SHIFT 0x00000000
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#define BIOS_DAC_TYPE__CRT 0x00000000
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#define BIOS_DAC_TYPE__NON_CRT 0x00000001
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#define BIOS_CONNECTOR_INFO__MUX_MASK 0x00000020
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#define BIOS_CONNECTOR_INFO__MUX_SHIFT 0x00000005
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#define BIOS_CHIPINFO_HEADER__CHIP_NUMBER__MASK 0xF0
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#define BIOS_CHIPINFO_HEADER__CHIP_NUMBER__SHIFT 0x00000004
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#define BIOS_CHIPINFO_HEADER__NUMBER_OF_CONNECTORS__MASK 0x0F
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#define BIOS_CHIPINFO_HEADER__NUMBER_OF_CONNECTORS__SHIFT 0x00000000
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#define BIOS_CHIPINFO__MAX_NUMBER_OF_CONNECTORS 0x00000010
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struct combios_connector_chip_info
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{
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uint8_t ucChipHeader;
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uint16_t sConnectorInfo[BIOS_CHIPINFO__MAX_NUMBER_OF_CONNECTORS];
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};
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#define BIOS_CONNECTOR_HEADER__NUMBER_OF_CHIPS__MASK 0xF0
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#define BIOS_CONNECTOR_HEADER__NUMBER_OF_CHIPS__SHIFT 0x00000004
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#define BIOS_CONNECTOR_HEADER__TABLE_REVISION__MASK 0x0F
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#define BIOS_CONNECTOR_HEADER__TABLE_REVISION__SHIFT 0x00000000
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struct combios_connector_table
|
||
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{
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||
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uint8_t ucConnectorHeader;
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struct combios_connector_chip_info sChipConnectorInfo[0x10];
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||
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};
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#pragma pack()
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||
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|
||
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int combios_parse(unsigned char *rom, struct combios_header *header);
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||
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#endif
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