444 lines
14 KiB
C
444 lines
14 KiB
C
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/*
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* Copyright 2007 Jérôme Glisse
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* Copyright 2007 Alex Deucher
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* Copyright 2007 Dave Airlie
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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/*
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* Authors:
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* Dave Airlie <airlied@linux.ie>
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "radeon_ms.h"
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struct radeon_pcie {
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uint32_t gart_table_size;
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struct drm_buffer_object *gart_table_object;
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volatile uint32_t *gart_table;
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struct drm_device *dev;
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unsigned long page_last;
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};
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struct radeon_pcie_gart {
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struct drm_ttm_backend backend;
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struct radeon_pcie *pcie;
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unsigned long page_first;
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struct page **pages;
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unsigned long num_pages;
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int populated;
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int bound;
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};
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static int pcie_ttm_bind(struct drm_ttm_backend *backend,
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struct drm_bo_mem_reg *bo_mem);
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static void pcie_ttm_clear(struct drm_ttm_backend *backend);
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static void pcie_ttm_destroy(struct drm_ttm_backend *backend);
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static int pcie_ttm_needs_ub_cache_adjust(struct drm_ttm_backend *backend);
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static int pcie_ttm_populate(struct drm_ttm_backend *backend,
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unsigned long num_pages, struct page **pages);
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static int pcie_ttm_unbind(struct drm_ttm_backend *backend);
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static struct drm_ttm_backend_func radeon_pcie_gart_ttm_backend =
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{
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.needs_ub_cache_adjust = pcie_ttm_needs_ub_cache_adjust,
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.populate = pcie_ttm_populate,
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.clear = pcie_ttm_clear,
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.bind = pcie_ttm_bind,
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.unbind = pcie_ttm_unbind,
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.destroy = pcie_ttm_destroy,
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};
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static void pcie_gart_flush(struct radeon_pcie *pcie)
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{
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struct drm_device *dev;
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struct drm_radeon_private *dev_priv;
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uint32_t flush;
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if (pcie == NULL) {
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return;
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}
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dev = pcie->dev;
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dev_priv = dev->dev_private;
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flush = dev_priv->driver_state.pcie_tx_gart_cntl;
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flush |= PCIE_TX_GART_CNTL__GART_INVALIDATE_TLB;
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PCIE_W(PCIE_TX_GART_CNTL, flush);
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PCIE_W(PCIE_TX_GART_CNTL, dev_priv->driver_state.pcie_tx_gart_cntl);
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}
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static __inline__ uint32_t pcie_gart_get_page_base(struct radeon_pcie *pcie,
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unsigned long page)
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{
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if (pcie == NULL || pcie->gart_table == NULL) {
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return 0;
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}
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return ((pcie->gart_table[page] & (~0xC)) << 8);
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}
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static __inline__ void pcie_gart_set_page_base(struct radeon_pcie *pcie,
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unsigned long page,
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uint32_t page_base)
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{
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if (pcie == NULL || pcie->gart_table == NULL) {
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return;
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}
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pcie->gart_table[page] = cpu_to_le32((page_base >> 8) | 0xC);
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}
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static int pcie_ttm_bind(struct drm_ttm_backend *backend,
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struct drm_bo_mem_reg *bo_mem)
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{
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struct radeon_pcie_gart *pcie_gart;
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unsigned long page_first;
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unsigned long page_last;
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unsigned long page, i;
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uint32_t page_base;
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pcie_gart = container_of(backend, struct radeon_pcie_gart, backend);
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page = page_first = bo_mem->mm_node->start;
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page_last = page_first + pcie_gart->num_pages;
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if (page_first >= pcie_gart->pcie->page_last ||
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page_last >= pcie_gart->pcie->page_last)
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return -EINVAL;
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while (page < page_last) {
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if (pcie_gart_get_page_base(pcie_gart->pcie, page)) {
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return -EBUSY;
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}
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page++;
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}
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for (i = 0, page = page_first; i < pcie_gart->num_pages; i++, page++) {
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struct page *cur_page = pcie_gart->pages[i];
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/* write value */
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page_base = page_to_phys(cur_page);
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pcie_gart_set_page_base(pcie_gart->pcie, page, page_base);
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}
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DRM_MEMORYBARRIER();
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pcie_gart_flush(pcie_gart->pcie);
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pcie_gart->bound = 1;
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pcie_gart->page_first = page_first;
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return 0;
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}
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static void pcie_ttm_clear(struct drm_ttm_backend *backend)
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{
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struct radeon_pcie_gart *pcie_gart;
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pcie_gart = container_of(backend, struct radeon_pcie_gart, backend);
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if (pcie_gart->pages) {
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backend->func->unbind(backend);
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pcie_gart->pages = NULL;
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}
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pcie_gart->num_pages = 0;
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}
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static void pcie_ttm_destroy(struct drm_ttm_backend *backend)
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{
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struct radeon_pcie_gart *pcie_gart;
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if (backend == NULL) {
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return;
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}
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pcie_gart = container_of(backend, struct radeon_pcie_gart, backend);
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if (pcie_gart->pages) {
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backend->func->clear(backend);
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}
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drm_ctl_free(pcie_gart, sizeof(*pcie_gart), DRM_MEM_TTM);
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}
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static int pcie_ttm_needs_ub_cache_adjust(struct drm_ttm_backend *backend)
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{
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return ((backend->flags & DRM_BE_FLAG_BOUND_CACHED) ? 0 : 1);
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}
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static int pcie_ttm_populate(struct drm_ttm_backend *backend,
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unsigned long num_pages, struct page **pages)
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{
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struct radeon_pcie_gart *pcie_gart;
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pcie_gart = container_of(backend, struct radeon_pcie_gart, backend);
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pcie_gart->pages = pages;
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pcie_gart->num_pages = num_pages;
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pcie_gart->populated = 1;
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return 0;
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}
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static int pcie_ttm_unbind(struct drm_ttm_backend *backend)
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{
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struct radeon_pcie_gart *pcie_gart;
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unsigned long page, i;
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pcie_gart = container_of(backend, struct radeon_pcie_gart, backend);
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if (pcie_gart->bound != 1 || pcie_gart->pcie->gart_table == NULL) {
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return -EINVAL;
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}
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for (i = 0, page = pcie_gart->page_first; i < pcie_gart->num_pages;
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i++, page++) {
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pcie_gart->pcie->gart_table[page] = 0;
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}
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pcie_gart_flush(pcie_gart->pcie);
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pcie_gart->bound = 0;
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pcie_gart->page_first = 0;
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return 0;
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}
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int radeon_ms_agp_finish(struct drm_device *dev)
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{
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drm_agp_release(dev);
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return 0;
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}
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int radeon_ms_agp_init(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_state *state = &dev_priv->driver_state;
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struct drm_agp_mode mode;
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uint32_t agp_status;
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int ret;
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if (dev->agp == NULL) {
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DRM_ERROR("[radeon_ms] can't initialize AGP\n");
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return -EINVAL;
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}
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ret = drm_agp_acquire(dev);
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if (ret) {
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DRM_ERROR("[radeon_ms] error failed to acquire agp\n");
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return ret;
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}
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agp_status = MMIO_R(AGP_STATUS);
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if ((AGP_STATUS__MODE_AGP30 & agp_status)) {
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mode.mode = AGP_STATUS__RATE4X;
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} else {
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mode.mode = AGP_STATUS__RATE2X_8X;
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}
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ret = drm_agp_enable(dev, mode);
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if (ret) {
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DRM_ERROR("[radeon_ms] error failed to enable agp\n");
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return ret;
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}
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state->agp_command = MMIO_R(AGP_COMMAND) | AGP_COMMAND__AGP_EN;
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state->agp_command &= ~AGP_COMMAND__FW_EN;
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state->agp_command &= ~AGP_COMMAND__MODE_4G_EN;
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state->aic_ctrl = 0;
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state->agp_base = REG_S(AGP_BASE, AGP_BASE_ADDR, dev->agp->base);
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state->agp_base_2 = 0;
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state->bus_cntl = MMIO_R(BUS_CNTL);
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state->bus_cntl &= ~BUS_CNTL__BUS_MASTER_DIS;
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state->mc_agp_location =
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REG_S(MC_AGP_LOCATION, MC_AGP_START,
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dev_priv->gpu_gart_start >> 16) |
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REG_S(MC_AGP_LOCATION, MC_AGP_TOP,
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dev_priv->gpu_gart_end >> 16);
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DRM_INFO("[radeon_ms] gpu agp base 0x%08X\n", MMIO_R(AGP_BASE));
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DRM_INFO("[radeon_ms] gpu agp location 0x%08X\n",
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MMIO_R(MC_AGP_LOCATION));
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DRM_INFO("[radeon_ms] gpu agp location 0x%08X\n",
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state->mc_agp_location);
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DRM_INFO("[radeon_ms] bus ready\n");
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return 0;
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}
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void radeon_ms_agp_restore(struct drm_device *dev, struct radeon_state *state)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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MMIO_W(MC_AGP_LOCATION, state->mc_agp_location);
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MMIO_W(AGP_BASE, state->agp_base);
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MMIO_W(AGP_BASE_2, state->agp_base_2);
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MMIO_W(AGP_COMMAND, state->agp_command);
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}
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void radeon_ms_agp_save(struct drm_device *dev, struct radeon_state *state)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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state->agp_command = MMIO_R(AGP_COMMAND);
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state->agp_base = MMIO_R(AGP_BASE);
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state->agp_base_2 = MMIO_R(AGP_BASE_2);
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state->mc_agp_location = MMIO_R(MC_AGP_LOCATION);
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}
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struct drm_ttm_backend *radeon_ms_pcie_create_ttm(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_pcie_gart *pcie_gart;
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pcie_gart = drm_ctl_calloc(1, sizeof (*pcie_gart), DRM_MEM_TTM);
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if (pcie_gart == NULL) {
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return NULL;
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}
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memset(pcie_gart, 0, sizeof(struct radeon_pcie_gart));
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pcie_gart->populated = 0;
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pcie_gart->pcie = dev_priv->bus;
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pcie_gart->backend.func = &radeon_pcie_gart_ttm_backend;
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return &pcie_gart->backend;
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}
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int radeon_ms_pcie_finish(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_pcie *pcie = dev_priv->bus;
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if (!dev_priv->bus_ready || pcie == NULL) {
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dev_priv->bus_ready = 0;
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return 0;
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}
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dev_priv->bus_ready = 0;
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if (pcie->gart_table) {
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drm_mem_reg_iounmap(dev, &pcie->gart_table_object->mem,
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(void *)pcie->gart_table);
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}
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pcie->gart_table = NULL;
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if (pcie->gart_table_object) {
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mutex_lock(&dev->struct_mutex);
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drm_bo_usage_deref_locked(&pcie->gart_table_object);
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mutex_unlock(&dev->struct_mutex);
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}
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dev_priv->bus = NULL;
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drm_free(pcie, sizeof(*pcie), DRM_MEM_DRIVER);
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return 0;
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}
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int radeon_ms_pcie_init(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_state *state = &dev_priv->driver_state;
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struct radeon_pcie *pcie;
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int ret = 0;
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/* allocate and clear device private structure */
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pcie = drm_alloc(sizeof(struct radeon_pcie), DRM_MEM_DRIVER);
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if (pcie == NULL) {
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return -ENOMEM;
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}
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memset(pcie, 0, sizeof(struct radeon_pcie));
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pcie->dev = dev;
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dev_priv->bus = (void *)pcie;
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pcie->gart_table_size = (dev_priv->gpu_gart_size / RADEON_PAGE_SIZE) *
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4;
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/* gart table start must be aligned on 16bytes, align it on one page */
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ret = drm_buffer_object_create(dev,
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||
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|
pcie->gart_table_size,
|
||
|
|
drm_bo_type_kernel,
|
||
|
|
DRM_BO_FLAG_READ |
|
||
|
|
DRM_BO_FLAG_WRITE |
|
||
|
|
DRM_BO_FLAG_MEM_VRAM |
|
||
|
|
DRM_BO_FLAG_NO_EVICT,
|
||
|
|
DRM_BO_HINT_DONT_FENCE,
|
||
|
|
1,
|
||
|
|
0,
|
||
|
|
&pcie->gart_table_object);
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
ret = drm_mem_reg_ioremap(dev, &pcie->gart_table_object->mem,
|
||
|
|
(void **) &pcie->gart_table);
|
||
|
|
if (ret) {
|
||
|
|
DRM_ERROR("[radeon_ms] error mapping gart table: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
DRM_INFO("[radeon_ms] gart table in vram at 0x%08lX\n",
|
||
|
|
pcie->gart_table_object->offset);
|
||
|
|
memset((void *)pcie->gart_table, 0, pcie->gart_table_size);
|
||
|
|
pcie->page_last = pcie->gart_table_size >> 2;
|
||
|
|
state->pcie_tx_gart_discard_rd_addr_lo =
|
||
|
|
REG_S(PCIE_TX_GART_DISCARD_RD_ADDR_LO,
|
||
|
|
GART_DISCARD_RD_ADDR_LO,
|
||
|
|
dev_priv->gpu_gart_start);
|
||
|
|
state->pcie_tx_gart_discard_rd_addr_hi =
|
||
|
|
REG_S(PCIE_TX_GART_DISCARD_RD_ADDR_HI,
|
||
|
|
GART_DISCARD_RD_ADDR_HI, 0);
|
||
|
|
state->pcie_tx_gart_base =
|
||
|
|
REG_S(PCIE_TX_GART_BASE, GART_BASE,
|
||
|
|
pcie->gart_table_object->offset);
|
||
|
|
state->pcie_tx_gart_start_lo =
|
||
|
|
REG_S(PCIE_TX_GART_START_LO, GART_START_LO,
|
||
|
|
dev_priv->gpu_gart_start);
|
||
|
|
state->pcie_tx_gart_start_hi =
|
||
|
|
REG_S(PCIE_TX_GART_START_HI, GART_START_HI, 0);
|
||
|
|
state->pcie_tx_gart_end_lo =
|
||
|
|
REG_S(PCIE_TX_GART_END_LO, GART_END_LO, dev_priv->gpu_gart_end);
|
||
|
|
state->pcie_tx_gart_end_hi =
|
||
|
|
REG_S(PCIE_TX_GART_END_HI, GART_END_HI, 0);
|
||
|
|
/* FIXME: why this ? */
|
||
|
|
state->aic_ctrl = 0;
|
||
|
|
state->agp_base = 0;
|
||
|
|
state->agp_base_2 = 0;
|
||
|
|
state->bus_cntl = MMIO_R(BUS_CNTL);
|
||
|
|
state->mc_agp_location = REG_S(MC_AGP_LOCATION, MC_AGP_START, 0xffc0) |
|
||
|
|
REG_S(MC_AGP_LOCATION, MC_AGP_TOP, 0xffff);
|
||
|
|
state->pcie_tx_gart_cntl =
|
||
|
|
PCIE_TX_GART_CNTL__GART_EN |
|
||
|
|
REG_S(PCIE_TX_GART_CNTL, GART_UNMAPPED_ACCESS,
|
||
|
|
GART_UNMAPPED_ACCESS__DISCARD) |
|
||
|
|
REG_S(PCIE_TX_GART_CNTL, GART_MODE, GART_MODE__CACHE_32x128) |
|
||
|
|
REG_S(PCIE_TX_GART_CNTL, GART_RDREQPATH_SEL,
|
||
|
|
GART_RDREQPATH_SEL__HDP);
|
||
|
|
DRM_INFO("[radeon_ms] gpu gart start 0x%08X\n",
|
||
|
|
PCIE_R(PCIE_TX_GART_START_LO));
|
||
|
|
DRM_INFO("[radeon_ms] gpu gart end 0x%08X\n",
|
||
|
|
PCIE_R(PCIE_TX_GART_END_LO));
|
||
|
|
DRM_INFO("[radeon_ms] bus ready\n");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void radeon_ms_pcie_restore(struct drm_device *dev, struct radeon_state *state)
|
||
|
|
{
|
||
|
|
struct drm_radeon_private *dev_priv = dev->dev_private;
|
||
|
|
|
||
|
|
/* disable gart before programing other registers */
|
||
|
|
radeon_ms_agp_restore(dev, state);
|
||
|
|
PCIE_W(PCIE_TX_GART_CNTL, 0);
|
||
|
|
PCIE_W(PCIE_TX_GART_BASE, state->pcie_tx_gart_base);
|
||
|
|
PCIE_W(PCIE_TX_GART_BASE, state->pcie_tx_gart_base);
|
||
|
|
PCIE_W(PCIE_TX_GART_DISCARD_RD_ADDR_HI,
|
||
|
|
state->pcie_tx_gart_discard_rd_addr_hi);
|
||
|
|
PCIE_W(PCIE_TX_GART_DISCARD_RD_ADDR_LO,
|
||
|
|
state->pcie_tx_gart_discard_rd_addr_lo);
|
||
|
|
PCIE_W(PCIE_TX_GART_START_HI, state->pcie_tx_gart_start_hi);
|
||
|
|
PCIE_W(PCIE_TX_GART_START_LO, state->pcie_tx_gart_start_lo);
|
||
|
|
PCIE_W(PCIE_TX_GART_END_HI, state->pcie_tx_gart_end_hi);
|
||
|
|
PCIE_W(PCIE_TX_GART_END_LO, state->pcie_tx_gart_end_lo);
|
||
|
|
PCIE_W(PCIE_TX_GART_CNTL, state->pcie_tx_gart_cntl);
|
||
|
|
}
|
||
|
|
|
||
|
|
void radeon_ms_pcie_save(struct drm_device *dev, struct radeon_state *state)
|
||
|
|
{
|
||
|
|
struct drm_radeon_private *dev_priv = dev->dev_private;
|
||
|
|
|
||
|
|
radeon_ms_agp_save(dev, state);
|
||
|
|
state->pcie_tx_gart_base = PCIE_R(PCIE_TX_GART_BASE);
|
||
|
|
state->pcie_tx_gart_base = PCIE_R(PCIE_TX_GART_BASE);
|
||
|
|
state->pcie_tx_gart_discard_rd_addr_hi =
|
||
|
|
PCIE_R(PCIE_TX_GART_DISCARD_RD_ADDR_HI);
|
||
|
|
state->pcie_tx_gart_discard_rd_addr_lo =
|
||
|
|
PCIE_R(PCIE_TX_GART_DISCARD_RD_ADDR_LO);
|
||
|
|
state->pcie_tx_gart_start_hi = PCIE_R(PCIE_TX_GART_START_HI);
|
||
|
|
state->pcie_tx_gart_start_lo = PCIE_R(PCIE_TX_GART_START_LO);
|
||
|
|
state->pcie_tx_gart_end_hi = PCIE_R(PCIE_TX_GART_END_HI);
|
||
|
|
state->pcie_tx_gart_end_lo = PCIE_R(PCIE_TX_GART_END_LO);
|
||
|
|
state->pcie_tx_gart_cntl = PCIE_R(PCIE_TX_GART_CNTL);
|
||
|
|
}
|