2004-08-23 19:44:37 -06:00
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/* via_dma.c -- DMA support for the VIA Unichrome/Pro
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*/
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/**************************************************************************
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2004-09-30 15:12:10 -06:00
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*
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2004-08-23 19:44:37 -06:00
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
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* All Rights Reserved.
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2004-09-30 15:12:10 -06:00
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*
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2004-08-23 19:44:37 -06:00
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**************************************************************************/
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#include "drmP.h"
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#include "drm.h"
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#include "via_drm.h"
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#include "via_drv.h"
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2004-09-07 10:48:44 -06:00
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#define VIA_2D_CMD 0xF0000000
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2004-08-23 19:44:37 -06:00
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static void via_cmdbuf_start(drm_via_private_t * dev_priv);
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static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
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static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
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static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
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2004-09-30 15:12:10 -06:00
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static int via_wait_idle(drm_via_private_t * dev_priv);
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2004-08-23 19:44:37 -06:00
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2004-08-25 21:54:01 -06:00
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static inline int
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via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
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{
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uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
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uint32_t cur_addr, hw_addr, next_addr;
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2004-09-30 15:12:10 -06:00
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volatile uint32_t *hw_addr_ptr;
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2004-08-25 21:54:01 -06:00
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uint32_t count;
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hw_addr_ptr = dev_priv->hw_addr_ptr;
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cur_addr = agp_base + dev_priv->dma_low;
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/* At high resolution (i.e. 1280x1024) and with high workload within
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* a short commmand stream, the following test will fail. It may be
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* that the engine is too busy to update hw_addr. Therefore, add
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* a large 64KB window between buffer head and tail.
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*/
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next_addr = cur_addr + size + 64 * 1024;
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2004-09-30 15:12:10 -06:00
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count = 1000000; /* How long is this? */
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2004-08-25 21:54:01 -06:00
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do {
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hw_addr = *hw_addr_ptr;
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if (count-- == 0) {
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2004-09-30 15:12:10 -06:00
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DRM_ERROR
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("via_cmdbuf_wait timed out hw %x dma_low %x\n",
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hw_addr, dev_priv->dma_low);
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2004-08-25 21:54:01 -06:00
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return -1;
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}
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} while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
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return 0;
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}
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/*
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* Checks whether buffer head has reach the end. Rewind the ring buffer
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* when necessary.
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*
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* Returns virtual pointer to ring buffer.
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*/
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2004-09-30 15:12:10 -06:00
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static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
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unsigned int size)
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2004-08-25 21:54:01 -06:00
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{
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if ((dev_priv->dma_low + size + 0x400) > dev_priv->dma_high) {
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via_cmdbuf_rewind(dev_priv);
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}
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if (via_cmdbuf_wait(dev_priv, size) != 0) {
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return NULL;
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}
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2004-09-30 15:12:10 -06:00
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return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
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2004-08-25 21:54:01 -06:00
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}
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2004-08-23 19:44:37 -06:00
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2004-09-30 15:12:10 -06:00
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int via_dma_cleanup(drm_device_t * dev)
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2004-08-23 19:44:37 -06:00
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{
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if (dev->dev_private) {
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2004-09-30 15:12:10 -06:00
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drm_via_private_t *dev_priv =
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(drm_via_private_t *) dev->dev_private;
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2004-08-23 19:44:37 -06:00
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if (dev_priv->ring.virtual_start) {
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via_cmdbuf_reset(dev_priv);
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2004-09-30 15:12:10 -06:00
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drm_core_ioremapfree(&dev_priv->ring.map, dev);
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2004-08-23 19:44:37 -06:00
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dev_priv->ring.virtual_start = NULL;
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}
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}
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return 0;
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}
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2004-09-30 15:12:10 -06:00
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static int via_initialize(drm_device_t * dev,
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drm_via_private_t * dev_priv,
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drm_via_dma_init_t * init)
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2004-08-23 19:44:37 -06:00
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{
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if (!dev_priv || !dev_priv->mmio) {
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DRM_ERROR("via_dma_init called before via_map_init\n");
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return DRM_ERR(EFAULT);
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}
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if (dev_priv->ring.virtual_start != NULL) {
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DRM_ERROR("%s called again without calling cleanup\n",
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2004-09-30 15:12:10 -06:00
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__FUNCTION__);
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2004-08-23 19:44:37 -06:00
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return DRM_ERR(EFAULT);
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}
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dev_priv->ring.map.offset = dev->agp->base + init->offset;
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dev_priv->ring.map.size = init->size;
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dev_priv->ring.map.type = 0;
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dev_priv->ring.map.flags = 0;
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dev_priv->ring.map.mtrr = 0;
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2004-09-30 15:12:10 -06:00
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drm_core_ioremap(&dev_priv->ring.map, dev);
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2004-08-23 19:44:37 -06:00
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if (dev_priv->ring.map.handle == NULL) {
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via_dma_cleanup(dev);
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DRM_ERROR("can not ioremap virtual address for"
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2004-09-30 15:12:10 -06:00
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" ring buffer\n");
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2004-08-23 19:44:37 -06:00
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return DRM_ERR(ENOMEM);
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}
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dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
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dev_priv->dma_ptr = dev_priv->ring.virtual_start;
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dev_priv->dma_low = 0;
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dev_priv->dma_high = init->size;
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dev_priv->dma_offset = init->offset;
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dev_priv->last_pause_ptr = NULL;
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dev_priv->hw_addr_ptr = dev_priv->mmio->handle + init->reg_pause_addr;
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via_cmdbuf_start(dev_priv);
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return 0;
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}
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2004-09-30 15:12:10 -06:00
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int via_dma_init(DRM_IOCTL_ARGS)
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2004-08-23 19:44:37 -06:00
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{
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DRM_DEVICE;
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2004-09-30 15:12:10 -06:00
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drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
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2004-08-23 19:44:37 -06:00
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drm_via_dma_init_t init;
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int retcode = 0;
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2004-09-30 15:12:10 -06:00
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DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t *) data,
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sizeof(init));
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2004-08-23 19:44:37 -06:00
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2004-09-30 15:12:10 -06:00
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switch (init.func) {
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2004-08-23 19:44:37 -06:00
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case VIA_INIT_DMA:
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retcode = via_initialize(dev, dev_priv, &init);
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break;
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case VIA_CLEANUP_DMA:
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retcode = via_dma_cleanup(dev);
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break;
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default:
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retcode = DRM_ERR(EINVAL);
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break;
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}
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return retcode;
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}
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2004-09-30 15:12:10 -06:00
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static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
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2004-08-23 19:44:37 -06:00
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{
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drm_via_private_t *dev_priv = dev->dev_private;
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2004-09-30 15:12:10 -06:00
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uint32_t *vb;
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2004-08-23 19:44:37 -06:00
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vb = via_check_dma(dev_priv, cmd->size);
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if (vb == NULL) {
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return DRM_ERR(EAGAIN);
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}
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2004-08-29 22:58:24 -06:00
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if (DRM_COPY_FROM_USER(vb, cmd->buf, cmd->size)) {
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return DRM_ERR(EFAULT);
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}
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2004-08-23 19:44:37 -06:00
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dev_priv->dma_low += cmd->size;
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via_cmdbuf_pause(dev_priv);
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return 0;
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}
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2004-09-30 15:12:10 -06:00
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static int via_quiescent(drm_device_t * dev)
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2004-08-23 19:44:37 -06:00
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{
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drm_via_private_t *dev_priv = dev->dev_private;
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if (!via_wait_idle(dev_priv)) {
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return DRM_ERR(EAGAIN);
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}
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return 0;
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}
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2004-09-30 15:12:10 -06:00
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int via_flush_ioctl(DRM_IOCTL_ARGS)
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2004-08-23 19:44:37 -06:00
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{
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DRM_DEVICE;
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2004-09-30 15:12:10 -06:00
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if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
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2004-08-23 19:44:37 -06:00
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DRM_ERROR("via_flush_ioctl called without lock held\n");
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return DRM_ERR(EINVAL);
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}
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2004-09-30 15:12:10 -06:00
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return via_quiescent(dev);
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2004-08-23 19:44:37 -06:00
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}
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2004-09-30 15:12:10 -06:00
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int via_cmdbuffer(DRM_IOCTL_ARGS)
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2004-08-23 19:44:37 -06:00
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{
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DRM_DEVICE;
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drm_via_cmdbuffer_t cmdbuf;
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int ret;
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2004-09-30 15:12:10 -06:00
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DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data,
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sizeof(cmdbuf));
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2004-08-23 19:44:37 -06:00
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DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
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2004-09-30 15:12:10 -06:00
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if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
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2004-08-23 19:44:37 -06:00
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DRM_ERROR("via_cmdbuffer called without lock held\n");
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return DRM_ERR(EINVAL);
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}
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2004-09-30 15:12:10 -06:00
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ret = via_dispatch_cmdbuffer(dev, &cmdbuf);
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2004-08-23 19:44:37 -06:00
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if (ret) {
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return ret;
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}
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return 0;
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}
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2004-09-30 15:12:10 -06:00
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static int via_parse_pci_cmdbuffer(drm_device_t * dev, const char *buf,
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unsigned int size)
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2004-09-07 10:48:44 -06:00
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{
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drm_via_private_t *dev_priv = dev->dev_private;
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uint32_t offset, value;
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2004-09-30 15:12:10 -06:00
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const uint32_t *regbuf = (uint32_t *) buf;
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2004-09-07 10:48:44 -06:00
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unsigned int i;
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2004-09-30 15:12:10 -06:00
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size >>= 3;
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for (i = 0; i < size; ++i) {
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offset = *regbuf;
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2004-09-07 10:48:44 -06:00
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regbuf += 2;
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2004-09-30 15:12:10 -06:00
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if ((offset > ((0x7FF >> 2) | VIA_2D_CMD)) &&
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(offset < ((0xC00 >> 2) | VIA_2D_CMD))) {
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2004-09-07 10:48:44 -06:00
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DRM_DEBUG("Attempt to access Burst Command Area.\n");
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2004-09-30 15:12:10 -06:00
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return DRM_ERR(EINVAL);
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2004-09-07 10:48:44 -06:00
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} else if (offset > ((0xDFF >> 2) | VIA_2D_CMD)) {
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DRM_DEBUG("Attempt to access DMA or VGA registers.\n");
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2004-09-30 15:12:10 -06:00
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return DRM_ERR(EINVAL);
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2004-09-07 10:48:44 -06:00
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}
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}
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2004-09-30 15:12:10 -06:00
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regbuf = (uint32_t *) buf;
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for (i = 0; i < size; ++i) {
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2004-09-07 10:48:44 -06:00
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offset = (*regbuf++ & ~VIA_2D_CMD) << 2;
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value = *regbuf++;
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2004-09-30 15:12:10 -06:00
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VIA_WRITE(offset, value);
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2004-09-07 10:48:44 -06:00
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}
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return 0;
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}
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2004-09-30 15:12:10 -06:00
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static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
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drm_via_cmdbuffer_t * cmd)
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2004-09-07 10:48:44 -06:00
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{
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drm_via_private_t *dev_priv = dev->dev_private;
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char *hugebuf;
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int ret;
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/*
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* We must be able to parse the buffer all at a time, so as
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* to return an error on an invalid operation without doing
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* anything.
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* Small buffers must, on the other hand be handled fast.
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*/
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2004-09-30 15:12:10 -06:00
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if (cmd->size > VIA_MAX_PCI_SIZE) {
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return DRM_ERR(ENOMEM);
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} else if (cmd->size > VIA_PREALLOCATED_PCI_SIZE) {
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if (NULL == (hugebuf = (char *)kmalloc(cmd->size, GFP_KERNEL)))
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return DRM_ERR(ENOMEM);
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if (DRM_COPY_FROM_USER(hugebuf, cmd->buf, cmd->size))
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2004-09-11 21:23:50 -06:00
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return DRM_ERR(EFAULT);
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2004-09-30 15:12:10 -06:00
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ret = via_parse_pci_cmdbuffer(dev, hugebuf, cmd->size);
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kfree(hugebuf);
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2004-09-07 10:48:44 -06:00
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} else {
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2004-09-30 15:12:10 -06:00
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if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
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2004-09-11 21:23:50 -06:00
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return DRM_ERR(EFAULT);
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2004-09-30 15:12:10 -06:00
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ret =
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via_parse_pci_cmdbuffer(dev, dev_priv->pci_buf, cmd->size);
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2004-09-07 10:48:44 -06:00
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}
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return ret;
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}
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2004-09-30 15:12:10 -06:00
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int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
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2004-09-07 10:48:44 -06:00
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{
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DRM_DEVICE;
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drm_via_cmdbuffer_t cmdbuf;
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int ret;
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2004-09-30 15:12:10 -06:00
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DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data,
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sizeof(cmdbuf));
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2004-09-07 10:48:44 -06:00
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2004-09-30 15:12:10 -06:00
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DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
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cmdbuf.size);
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2004-09-07 10:48:44 -06:00
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2004-09-30 15:12:10 -06:00
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|
|
if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
|
2004-09-07 10:48:44 -06:00
|
|
|
DRM_ERROR("via_pci_cmdbuffer called without lock held\n");
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf);
|
2004-09-07 10:48:44 -06:00
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-23 19:44:37 -06:00
|
|
|
/************************************************************************/
|
|
|
|
#include "via_3d_reg.h"
|
|
|
|
|
|
|
|
#define CMDBUF_ALIGNMENT_SIZE (0x100)
|
|
|
|
#define CMDBUF_ALIGNMENT_MASK (0xff)
|
|
|
|
|
|
|
|
/* defines for VIA 3D registers */
|
|
|
|
#define VIA_REG_STATUS 0x400
|
|
|
|
#define VIA_REG_TRANSET 0x43C
|
|
|
|
#define VIA_REG_TRANSPACE 0x440
|
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
/* VIA_REG_STATUS(0x400): Engine Status */
|
|
|
|
#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
|
|
|
|
#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
|
|
|
|
#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
|
|
|
|
#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
#define SetReg2DAGP(nReg, nData) { \
|
|
|
|
*((uint32_t *)(vb)) = ((nReg) >> 2) | 0xF0000000; \
|
|
|
|
*((uint32_t *)(vb) + 1) = (nData); \
|
|
|
|
vb = ((uint32_t *)vb) + 2; \
|
|
|
|
dev_priv->dma_low +=8; \
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t via_swap_count = 0;
|
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
|
|
|
|
uint32_t * vb, int qw_count)
|
2004-08-23 19:44:37 -06:00
|
|
|
{
|
2004-09-30 15:12:10 -06:00
|
|
|
for (; qw_count > 0; --qw_count) {
|
2004-08-23 19:44:37 -06:00
|
|
|
*vb++ = (0xcc000000 | (dev_priv->dma_low & 0xffffff));
|
|
|
|
*vb++ = (0xdd400000 | via_swap_count);
|
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
}
|
|
|
|
via_swap_count = (via_swap_count + 1) & 0xffff;
|
|
|
|
return vb;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is used internally by ring buffer mangement code.
|
|
|
|
*
|
|
|
|
* Returns virtual pointer to ring buffer.
|
|
|
|
*/
|
2004-09-30 15:12:10 -06:00
|
|
|
static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
|
2004-08-23 19:44:37 -06:00
|
|
|
{
|
2004-09-30 15:12:10 -06:00
|
|
|
return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
|
2004-08-23 19:44:37 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int via_wait_idle(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
int count = 10000000;
|
|
|
|
while (count-- && (VIA_READ(VIA_REG_STATUS) &
|
2004-09-30 15:12:10 -06:00
|
|
|
(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
|
|
|
|
VIA_3D_ENG_BUSY))) ;
|
2004-08-23 19:44:37 -06:00
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
|
2004-08-23 19:44:37 -06:00
|
|
|
{
|
2004-09-30 15:12:10 -06:00
|
|
|
uint32_t *vb = via_get_dma(dev_priv);
|
|
|
|
/* GEDST */
|
2004-08-23 19:44:37 -06:00
|
|
|
SetReg2DAGP(0x0C, (0 | (0 << 16)));
|
2004-09-30 15:12:10 -06:00
|
|
|
/* GEWD */
|
2004-08-23 19:44:37 -06:00
|
|
|
SetReg2DAGP(0x10, 0 | (0 << 16));
|
2004-09-30 15:12:10 -06:00
|
|
|
/* BITBLT */
|
2004-08-23 19:44:37 -06:00
|
|
|
SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void via_cmdbuf_start(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
uint32_t agp_base;
|
|
|
|
uint32_t pause_addr, pause_addr_lo, pause_addr_hi;
|
|
|
|
uint32_t start_addr, start_addr_lo;
|
|
|
|
uint32_t end_addr, end_addr_lo;
|
|
|
|
uint32_t qw_pad_count;
|
|
|
|
uint32_t command;
|
2004-09-30 15:12:10 -06:00
|
|
|
uint32_t *vb;
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
dev_priv->dma_low = 0;
|
|
|
|
vb = via_get_dma(dev_priv);
|
|
|
|
|
|
|
|
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
|
|
|
|
start_addr = agp_base;
|
|
|
|
end_addr = agp_base + dev_priv->dma_high;
|
|
|
|
|
|
|
|
start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
|
|
|
|
end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
|
|
|
|
command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
|
2004-09-30 15:12:10 -06:00
|
|
|
((end_addr & 0xff000000) >> 16));
|
2004-08-23 19:44:37 -06:00
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
|
|
|
|
(VIA_REG_TRANSPACE >> 2);
|
|
|
|
*vb++ = (HC_ParaType_PreCR << 16);
|
2004-08-23 19:44:37 -06:00
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
|
|
|
|
((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
|
2004-08-23 19:44:37 -06:00
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
|
|
|
|
pause_addr_lo = ((HC_SubA_HAGPBpL << 24) |
|
|
|
|
HC_HAGPBpID_PAUSE | (pause_addr & 0xffffff));
|
|
|
|
pause_addr_hi = ((HC_SubA_HAGPBpH << 24) | (pause_addr >> 24));
|
2004-08-23 19:44:37 -06:00
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
*vb++ = pause_addr_hi;
|
|
|
|
*vb++ = pause_addr_lo;
|
|
|
|
dev_priv->dma_low += 8;
|
2004-09-30 15:12:10 -06:00
|
|
|
dev_priv->last_pause_ptr = vb - 1;
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, command);
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
|
|
|
|
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
|
|
|
|
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
uint32_t agp_base;
|
|
|
|
uint32_t pause_addr, pause_addr_lo, pause_addr_hi;
|
|
|
|
uint32_t start_addr;
|
|
|
|
uint32_t end_addr, end_addr_lo;
|
2004-09-30 15:12:10 -06:00
|
|
|
uint32_t *vb;
|
2004-08-23 19:44:37 -06:00
|
|
|
uint32_t qw_pad_count;
|
|
|
|
uint32_t command;
|
|
|
|
uint32_t jump_addr, jump_addr_lo, jump_addr_hi;
|
|
|
|
|
|
|
|
/* Seems like Unichrome has bug that when the PAUSE register is
|
|
|
|
* set in the AGP command stream immediately after a PCI write to
|
|
|
|
* the same register, the command regulator goes into a looping
|
|
|
|
* state. Prepending a BitBLT command to stall the command
|
|
|
|
* regulator for a moment seems to solve the problem.
|
|
|
|
*/
|
|
|
|
via_cmdbuf_wait(dev_priv, 48);
|
|
|
|
via_dummy_bitblt(dev_priv);
|
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
/* At end of buffer, rewind with a JUMP command. */
|
|
|
|
vb = via_get_dma(dev_priv);
|
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
|
|
|
|
(VIA_REG_TRANSPACE >> 2);
|
|
|
|
*vb++ = (HC_ParaType_PreCR << 16);
|
2004-08-23 19:44:37 -06:00
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
|
|
|
|
((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
|
|
|
|
start_addr = agp_base;
|
2004-09-30 15:12:10 -06:00
|
|
|
end_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
jump_addr = end_addr;
|
2004-09-30 15:12:10 -06:00
|
|
|
jump_addr_lo = ((HC_SubA_HAGPBpL << 24) | HC_HAGPBpID_JUMP |
|
2004-08-23 19:44:37 -06:00
|
|
|
(jump_addr & 0xffffff));
|
2004-09-30 15:12:10 -06:00
|
|
|
jump_addr_hi = ((HC_SubA_HAGPBpH << 24) | (jump_addr >> 24));
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
|
|
|
|
command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
|
2004-09-30 15:12:10 -06:00
|
|
|
((end_addr & 0xff000000) >> 16));
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
*vb++ = command;
|
|
|
|
*vb++ = end_addr_lo;
|
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
/* Now at beginning of buffer, make sure engine will pause here. */
|
|
|
|
dev_priv->dma_low = 0;
|
|
|
|
if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
|
|
|
|
DRM_ERROR("via_cmdbuf_jump failed\n");
|
|
|
|
}
|
|
|
|
vb = via_get_dma(dev_priv);
|
|
|
|
|
|
|
|
end_addr = agp_base + dev_priv->dma_high;
|
|
|
|
|
|
|
|
end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
|
|
|
|
command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
|
2004-09-30 15:12:10 -06:00
|
|
|
((end_addr & 0xff000000) >> 16));
|
2004-08-23 19:44:37 -06:00
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
|
|
|
|
((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
|
2004-08-23 19:44:37 -06:00
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
|
|
|
|
pause_addr_lo = ((HC_SubA_HAGPBpL << 24) | HC_HAGPBpID_PAUSE |
|
|
|
|
(pause_addr & 0xffffff));
|
|
|
|
pause_addr_hi = ((HC_SubA_HAGPBpH << 24) | (pause_addr >> 24));
|
2004-08-23 19:44:37 -06:00
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
|
|
|
|
(VIA_REG_TRANSPACE >> 2);
|
|
|
|
*vb++ = (HC_ParaType_PreCR << 16);
|
2004-08-23 19:44:37 -06:00
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
|
|
|
|
*vb++ = pause_addr_hi;
|
|
|
|
*vb++ = pause_addr_lo;
|
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
|
|
|
|
*vb++ = command;
|
|
|
|
*vb++ = end_addr_lo;
|
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
|
|
|
|
vb = via_align_buffer(dev_priv, vb, qw_pad_count - 4);
|
|
|
|
|
|
|
|
*vb++ = pause_addr_hi;
|
|
|
|
*vb++ = pause_addr_lo;
|
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
|
|
|
|
*dev_priv->last_pause_ptr = jump_addr_lo;
|
2004-09-30 15:12:10 -06:00
|
|
|
dev_priv->last_pause_ptr = vb - 1;
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
if (VIA_READ(0x41c) & 0x80000000) {
|
|
|
|
VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, jump_addr_hi);
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, jump_addr_lo);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
via_cmdbuf_pause(dev_priv);
|
|
|
|
via_cmdbuf_jump(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
|
|
|
|
{
|
|
|
|
uint32_t agp_base;
|
|
|
|
uint32_t pause_addr, pause_addr_lo, pause_addr_hi;
|
2004-09-30 15:12:10 -06:00
|
|
|
uint32_t *vb;
|
2004-08-23 19:44:37 -06:00
|
|
|
uint32_t qw_pad_count;
|
|
|
|
|
|
|
|
via_cmdbuf_wait(dev_priv, 0x200);
|
|
|
|
|
|
|
|
vb = via_get_dma(dev_priv);
|
2004-09-30 15:12:10 -06:00
|
|
|
*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
|
|
|
|
(VIA_REG_TRANSPACE >> 2);
|
|
|
|
*vb++ = (HC_ParaType_PreCR << 16);
|
2004-08-23 19:44:37 -06:00
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
|
|
|
|
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
|
2004-09-30 15:12:10 -06:00
|
|
|
qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
|
|
|
|
((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
|
2004-08-23 19:44:37 -06:00
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
|
|
|
|
pause_addr_lo = ((HC_SubA_HAGPBpL << 24) | cmd_type |
|
|
|
|
(pause_addr & 0xffffff));
|
|
|
|
pause_addr_hi = ((HC_SubA_HAGPBpH << 24) | (pause_addr >> 24));
|
2004-08-23 19:44:37 -06:00
|
|
|
|
2004-09-30 15:12:10 -06:00
|
|
|
vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
*vb++ = pause_addr_hi;
|
|
|
|
*vb++ = pause_addr_lo;
|
|
|
|
dev_priv->dma_low += 8;
|
|
|
|
*dev_priv->last_pause_ptr = pause_addr_lo;
|
2004-09-30 15:12:10 -06:00
|
|
|
dev_priv->last_pause_ptr = vb - 1;
|
2004-08-23 19:44:37 -06:00
|
|
|
|
|
|
|
if (VIA_READ(0x41c) & 0x80000000) {
|
|
|
|
VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
|
|
|
|
via_wait_idle(dev_priv);
|
|
|
|
}
|