303 lines
9.7 KiB
C
303 lines
9.7 KiB
C
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/*
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* Copyright <EFBFBD> 2006 Intel Corporation
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*/
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/**
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* @file SDVO command definitions and structures.
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*/
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#define SDVO_OUTPUT_FIRST (0)
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#define SDVO_OUTPUT_TMDS0 (1 << 0)
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#define SDVO_OUTPUT_RGB0 (1 << 1)
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#define SDVO_OUTPUT_CVBS0 (1 << 2)
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#define SDVO_OUTPUT_SVID0 (1 << 3)
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#define SDVO_OUTPUT_YPRPB0 (1 << 4)
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#define SDVO_OUTPUT_SCART0 (1 << 5)
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#define SDVO_OUTPUT_LVDS0 (1 << 6)
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#define SDVO_OUTPUT_TMDS1 (1 << 8)
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#define SDVO_OUTPUT_RGB1 (1 << 13)
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#define SDVO_OUTPUT_LVDS1 (1 << 14)
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#define SDVO_OUTPUT_LAST (14)
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struct intel_sdvo_caps {
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u8 vendor_id;
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u8 device_id;
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u8 device_rev_id;
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u8 sdvo_version_major;
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u8 sdvo_version_minor;
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unsigned int sdvo_inputs_mask:2;
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unsigned int smooth_scaling:1;
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unsigned int sharp_scaling:1;
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unsigned int up_scaling:1;
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unsigned int down_scaling:1;
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unsigned int stall_support:1;
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unsigned int pad:1;
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u16 output_flags;
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} __attribute__((packed));
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/** This matches the EDID DTD structure, more or less */
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struct intel_sdvo_dtd {
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struct {
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u16 clock; /**< pixel clock, in 10kHz units */
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u8 h_active; /**< lower 8 bits (pixels) */
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u8 h_blank; /**< lower 8 bits (pixels) */
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u8 h_high; /**< upper 4 bits each h_active, h_blank */
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u8 v_active; /**< lower 8 bits (lines) */
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u8 v_blank; /**< lower 8 bits (lines) */
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u8 v_high; /**< upper 4 bits each v_active, v_blank */
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} part1;
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struct {
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u8 h_sync_off; /**< lower 8 bits, from hblank start */
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u8 h_sync_width; /**< lower 8 bits (pixels) */
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/** lower 4 bits each vsync offset, vsync width */
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u8 v_sync_off_width;
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/**
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* 2 high bits of hsync offset, 2 high bits of hsync width,
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* bits 4-5 of vsync offset, and 2 high bits of vsync width.
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*/
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u8 sync_off_width_high;
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u8 dtd_flags;
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u8 sdvo_flags;
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/** bits 6-7 of vsync offset at bits 6-7 */
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u8 v_sync_off_high;
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u8 reserved;
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} part2;
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} __attribute__((packed));
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struct intel_sdvo_pixel_clock_range {
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u16 min; /**< pixel clock, in 10kHz units */
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u16 max; /**< pixel clock, in 10kHz units */
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} __attribute__((packed));
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struct intel_sdvo_preferred_input_timing_args {
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u16 clock;
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u16 width;
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u16 height;
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} __attribute__((packed));
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/* I2C registers for SDVO */
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#define SDVO_I2C_ARG_0 0x07
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#define SDVO_I2C_ARG_1 0x06
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#define SDVO_I2C_ARG_2 0x05
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#define SDVO_I2C_ARG_3 0x04
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#define SDVO_I2C_ARG_4 0x03
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#define SDVO_I2C_ARG_5 0x02
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#define SDVO_I2C_ARG_6 0x01
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#define SDVO_I2C_ARG_7 0x00
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#define SDVO_I2C_OPCODE 0x08
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#define SDVO_I2C_CMD_STATUS 0x09
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#define SDVO_I2C_RETURN_0 0x0a
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#define SDVO_I2C_RETURN_1 0x0b
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#define SDVO_I2C_RETURN_2 0x0c
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#define SDVO_I2C_RETURN_3 0x0d
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#define SDVO_I2C_RETURN_4 0x0e
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#define SDVO_I2C_RETURN_5 0x0f
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#define SDVO_I2C_RETURN_6 0x10
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#define SDVO_I2C_RETURN_7 0x11
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#define SDVO_I2C_VENDOR_BEGIN 0x20
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/* Status results */
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#define SDVO_CMD_STATUS_POWER_ON 0x0
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#define SDVO_CMD_STATUS_SUCCESS 0x1
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#define SDVO_CMD_STATUS_NOTSUPP 0x2
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#define SDVO_CMD_STATUS_INVALID_ARG 0x3
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#define SDVO_CMD_STATUS_PENDING 0x4
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#define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5
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#define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6
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/* SDVO commands, argument/result registers */
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#define SDVO_CMD_RESET 0x01
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/** Returns a struct intel_sdvo_caps */
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#define SDVO_CMD_GET_DEVICE_CAPS 0x02
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#define SDVO_CMD_GET_FIRMWARE_REV 0x86
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# define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0
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# define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1
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# define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2
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/**
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* Reports which inputs are trained (managed to sync).
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*
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* Devices must have trained within 2 vsyncs of a mode change.
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*/
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#define SDVO_CMD_GET_TRAINED_INPUTS 0x03
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struct intel_sdvo_get_trained_inputs_response {
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unsigned int input0_trained:1;
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unsigned int input1_trained:1;
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unsigned int pad:6;
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} __attribute__((packed));
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/** Returns a struct intel_sdvo_output_flags of active outputs. */
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#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
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/**
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* Sets the current set of active outputs.
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*
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* Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP
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* on multi-output devices.
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*/
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#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05
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/**
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* Returns the current mapping of SDVO inputs to outputs on the device.
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*
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* Returns two struct intel_sdvo_output_flags structures.
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*/
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#define SDVO_CMD_GET_IN_OUT_MAP 0x06
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/**
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* Sets the current mapping of SDVO inputs to outputs on the device.
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*
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* Takes two struct i380_sdvo_output_flags structures.
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*/
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#define SDVO_CMD_SET_IN_OUT_MAP 0x07
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/**
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* Returns a struct intel_sdvo_output_flags of attached displays.
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*/
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#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b
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/**
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* Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.
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*/
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#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c
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/**
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* Takes a struct intel_sdvo_output_flags.
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*/
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#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d
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/**
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* Returns a struct intel_sdvo_output_flags of displays with hot plug
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* interrupts enabled.
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*/
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#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e
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#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
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struct intel_sdvo_get_interrupt_event_source_response {
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u16 interrupt_status;
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unsigned int ambient_light_interrupt:1;
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unsigned int pad:7;
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} __attribute__((packed));
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/**
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* Selects which input is affected by future input commands.
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*
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* Commands affected include SET_INPUT_TIMINGS_PART[12],
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* GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
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* GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
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*/
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#define SDVO_CMD_SET_TARGET_INPUT 0x10
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struct intel_sdvo_set_target_input_args {
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unsigned int target_1:1;
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unsigned int pad:7;
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} __attribute__((packed));
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/**
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* Takes a struct intel_sdvo_output_flags of which outputs are targetted by
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* future output commands.
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*
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* Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
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* GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
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*/
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#define SDVO_CMD_SET_TARGET_OUTPUT 0x11
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#define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12
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#define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13
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#define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14
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#define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15
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#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16
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#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17
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#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18
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#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19
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/* Part 1 */
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# define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0
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# define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1
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# define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2
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# define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3
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# define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4
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# define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5
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# define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6
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# define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7
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/* Part 2 */
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# define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0
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# define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1
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# define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2
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# define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3
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# define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4
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# define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7)
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# define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5)
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# define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3)
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# define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1)
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# define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5
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# define SDVO_DTD_SDVO_FLAG_STALL (1 << 7)
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# define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6)
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# define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6)
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# define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4)
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# define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4)
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# define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4)
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# define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4)
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# define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6
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/**
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* Generates a DTD based on the given width, height, and flags.
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*
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* This will be supported by any device supporting scaling or interlaced
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* modes.
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*/
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#define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a
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# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0
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# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1
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# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2
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# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3
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# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4
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# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5
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# define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6
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# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0)
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# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1)
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#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b
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#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c
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/** Returns a struct intel_sdvo_pixel_clock_range */
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#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d
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/** Returns a struct intel_sdvo_pixel_clock_range */
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#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e
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/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
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#define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f
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/** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
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#define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20
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/** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
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#define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21
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# define SDVO_CLOCK_RATE_MULT_1X (1 << 0)
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# define SDVO_CLOCK_RATE_MULT_2X (1 << 1)
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# define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
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#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
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#define SDVO_CMD_GET_TV_FORMAT 0x28
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#define SDVO_CMD_SET_TV_FORMAT 0x29
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#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
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#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
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#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
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# define SDVO_ENCODER_STATE_ON (1 << 0)
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# define SDVO_ENCODER_STATE_STANDBY (1 << 1)
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# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
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# define SDVO_ENCODER_STATE_OFF (1 << 3)
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#define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93
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#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
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# define SDVO_CONTROL_BUS_PROM 0x0
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# define SDVO_CONTROL_BUS_DDC1 0x1
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# define SDVO_CONTROL_BUS_DDC2 0x2
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# define SDVO_CONTROL_BUS_DDC3 0x3
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