2006-08-21 13:36:00 -06:00
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/**************************************************************************
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*
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* Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*
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**************************************************************************/
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/*
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* Authors: Thomas Hellstr<EFBFBD>m <thomas-at-tungstengraphics-dot-com>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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/*
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* Implements an intel sync flush operation.
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*/
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2007-07-15 20:32:51 -06:00
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static void i915_perform_flush(struct drm_device * dev)
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2006-08-21 13:36:00 -06:00
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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2007-07-15 21:37:02 -06:00
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struct drm_fence_manager *fm = &dev->fm;
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2007-09-12 07:50:38 -06:00
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struct drm_fence_class_manager *fc = &fm->fence_class[0];
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2007-07-15 21:37:02 -06:00
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struct drm_fence_driver *driver = dev->driver->fence_driver;
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2006-08-21 13:36:00 -06:00
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uint32_t flush_flags = 0;
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uint32_t flush_sequence = 0;
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uint32_t i_status;
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uint32_t diff;
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uint32_t sequence;
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2007-02-22 09:04:20 -07:00
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int rwflush;
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2006-08-21 13:36:00 -06:00
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2006-09-25 03:51:08 -06:00
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if (!dev_priv)
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return;
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2007-02-15 04:10:33 -07:00
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if (fc->pending_exe_flush) {
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2006-08-21 13:36:00 -06:00
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sequence = READ_BREADCRUMB(dev_priv);
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2006-09-15 03:18:35 -06:00
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/*
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* First update fences with the current breadcrumb.
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*/
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2007-06-15 09:13:11 -06:00
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diff = (sequence - fc->last_exe_flush) & BREADCRUMB_MASK;
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2006-08-21 13:36:00 -06:00
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if (diff < driver->wrap_diff && diff != 0) {
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2007-02-14 05:31:35 -07:00
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drm_fence_handler(dev, 0, sequence, DRM_FENCE_TYPE_EXE);
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2006-10-17 11:57:06 -06:00
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}
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2006-09-08 09:24:38 -06:00
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2007-02-22 09:04:20 -07:00
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if (dev_priv->fence_irq_on && !fc->pending_exe_flush) {
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i915_user_irq_off(dev_priv);
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dev_priv->fence_irq_on = 0;
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} else if (!dev_priv->fence_irq_on && fc->pending_exe_flush) {
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2006-09-08 09:24:38 -06:00
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i915_user_irq_on(dev_priv);
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dev_priv->fence_irq_on = 1;
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2006-08-21 13:36:00 -06:00
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}
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}
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2006-09-15 03:18:35 -06:00
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2006-08-21 13:36:00 -06:00
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if (dev_priv->flush_pending) {
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i_status = READ_HWSP(dev_priv, 0);
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if ((i_status & (1 << 12)) !=
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(dev_priv->saved_flush_status & (1 << 12))) {
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flush_flags = dev_priv->flush_flags;
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flush_sequence = dev_priv->flush_sequence;
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dev_priv->flush_pending = 0;
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2007-02-14 05:31:35 -07:00
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drm_fence_handler(dev, 0, flush_sequence, flush_flags);
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2006-10-17 11:57:06 -06:00
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}
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2006-08-21 13:36:00 -06:00
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}
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2006-09-15 03:18:35 -06:00
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2007-02-22 09:04:20 -07:00
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rwflush = fc->pending_flush & DRM_I915_FENCE_TYPE_RW;
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if (rwflush && !dev_priv->flush_pending) {
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2006-08-21 13:36:00 -06:00
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dev_priv->flush_sequence = (uint32_t) READ_BREADCRUMB(dev_priv);
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2007-02-15 04:10:33 -07:00
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dev_priv->flush_flags = fc->pending_flush;
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2006-08-21 13:36:00 -06:00
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dev_priv->saved_flush_status = READ_HWSP(dev_priv, 0);
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I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
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dev_priv->flush_pending = 1;
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2007-02-22 09:04:20 -07:00
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fc->pending_flush &= ~DRM_I915_FENCE_TYPE_RW;
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2006-08-21 13:36:00 -06:00
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}
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2006-09-15 03:18:35 -06:00
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if (dev_priv->flush_pending) {
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i_status = READ_HWSP(dev_priv, 0);
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if ((i_status & (1 << 12)) !=
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(dev_priv->saved_flush_status & (1 << 12))) {
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flush_flags = dev_priv->flush_flags;
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flush_sequence = dev_priv->flush_sequence;
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dev_priv->flush_pending = 0;
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2007-02-14 05:31:35 -07:00
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drm_fence_handler(dev, 0, flush_sequence, flush_flags);
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2006-10-17 11:57:06 -06:00
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}
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2006-09-15 03:18:35 -06:00
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}
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2006-08-21 13:36:00 -06:00
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}
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2007-07-15 20:32:51 -06:00
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void i915_poke_flush(struct drm_device * dev, uint32_t class)
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2006-08-21 13:36:00 -06:00
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{
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2007-07-15 21:37:02 -06:00
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struct drm_fence_manager *fm = &dev->fm;
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2006-08-21 13:36:00 -06:00
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unsigned long flags;
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write_lock_irqsave(&fm->lock, flags);
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i915_perform_flush(dev);
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write_unlock_irqrestore(&fm->lock, flags);
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}
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2007-07-15 20:32:51 -06:00
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int i915_fence_emit_sequence(struct drm_device * dev, uint32_t class, uint32_t flags,
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2006-10-17 11:57:06 -06:00
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uint32_t * sequence, uint32_t * native_type)
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2006-08-21 13:36:00 -06:00
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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2006-10-19 08:58:00 -06:00
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if (!dev_priv)
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return -EINVAL;
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2006-08-21 13:36:00 -06:00
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i915_emit_irq(dev);
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*sequence = (uint32_t) dev_priv->counter;
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2006-10-17 11:57:06 -06:00
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*native_type = DRM_FENCE_TYPE_EXE;
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if (flags & DRM_I915_FENCE_FLAG_FLUSHED)
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2006-09-15 08:47:09 -06:00
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*native_type |= DRM_I915_FENCE_TYPE_RW;
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2006-10-17 11:57:06 -06:00
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2006-08-21 13:36:00 -06:00
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return 0;
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}
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2007-07-15 20:32:51 -06:00
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void i915_fence_handler(struct drm_device * dev)
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2006-08-21 13:36:00 -06:00
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{
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2007-07-15 21:37:02 -06:00
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struct drm_fence_manager *fm = &dev->fm;
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2006-08-21 13:36:00 -06:00
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write_lock(&fm->lock);
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i915_perform_flush(dev);
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write_unlock(&fm->lock);
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}
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2007-02-14 05:31:35 -07:00
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2007-07-15 20:32:51 -06:00
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int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags)
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2007-02-14 05:31:35 -07:00
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{
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/*
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* We have an irq that tells us when we have a new breadcrumb.
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*/
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if (class == 0 && flags == DRM_FENCE_TYPE_EXE)
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return 1;
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return 0;
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}
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