80 lines
3.2 KiB
C
80 lines
3.2 KiB
C
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/****************************************************************************
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* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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* *
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* All Rights Reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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* *
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
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* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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***************************************************************************/
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#ifndef _XGI_CMDLIST_H_
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#define _XGI_CMDLIST_H_
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#define ONE_BIT_MASK 0x1
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#define TWENTY_BIT_MASK 0xfffff
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#define M2REG_FLUSH_2D_ENGINE_MASK (ONE_BIT_MASK<<20)
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#define M2REG_FLUSH_3D_ENGINE_MASK TWENTY_BIT_MASK
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#define M2REG_FLUSH_FLIP_ENGINE_MASK (ONE_BIT_MASK<<21)
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#define BASE_3D_ENG 0x2800
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#define M2REG_AUTO_LINK_SETTING_ADDRESS 0x10
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#define M2REG_CLEAR_COUNTERS_MASK (ONE_BIT_MASK<<4)
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#define M2REG_PCI_TRIGGER_MODE_MASK (ONE_BIT_MASK<<1)
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#define BEGIN_VALID_MASK (ONE_BIT_MASK<<20)
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#define BEGIN_LINK_ENABLE_MASK (ONE_BIT_MASK<<31)
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#define M2REG_PCI_TRIGGER_REGISTER_ADDRESS 0x14
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typedef enum
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{
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FLUSH_2D = M2REG_FLUSH_2D_ENGINE_MASK,
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FLUSH_3D = M2REG_FLUSH_3D_ENGINE_MASK,
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FLUSH_FLIP = M2REG_FLUSH_FLIP_ENGINE_MASK
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}FLUSH_CODE;
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typedef enum
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{
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AGPCMDLIST_SCRATCH_SIZE = 0x100,
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AGPCMDLIST_BEGIN_SIZE = 0x004,
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AGPCMDLIST_3D_SCRATCH_CMD_SIZE = 0x004,
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AGPCMDLIST_2D_SCRATCH_CMD_SIZE = 0x00c,
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AGPCMDLIST_FLUSH_CMD_LEN = 0x004,
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AGPCMDLIST_DUMY_END_BATCH_LEN = AGPCMDLIST_BEGIN_SIZE
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}CMD_SIZE;
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typedef struct xgi_cmdring_info_s
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{
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U32 _cmdRingSize;
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U32 _cmdRingBuffer;
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U32 _cmdRingBusAddr;
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U32 _lastBatchStartAddr;
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U32 _cmdRingOffset;
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}xgi_cmdring_info_t;
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extern int xgi_cmdlist_initialize(xgi_info_t *info, U32 size);
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extern void xgi_submit_cmdlist(xgi_info_t *info, xgi_cmd_info_t * pCmdInfo);
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extern void xgi_state_change(xgi_info_t *info, xgi_state_info_t * pStateInfo);
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extern void xgi_cmdlist_cleanup(xgi_info_t *info);
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#endif /* _XGI_CMDLIST_H_ */
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