2002-04-09 15:54:56 -06:00
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/* xf86drmCompat.c -- User-level interface to old DRM device drivers
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*
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* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Backwards compatability modules broken out by:
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* Jens Owen <jens@tungstengraphics.com>
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*
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*/
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2003-03-24 17:29:14 -07:00
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/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drmCompat.c,v 1.1 2002/10/30 12:52:33 alanh Exp $ */
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2002-04-09 15:54:56 -06:00
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#ifdef XFree86Server
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# include "xf86.h"
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# include "xf86_OSproc.h"
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# include "xf86_ansic.h"
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# define _DRM_MALLOC xalloc
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# define _DRM_FREE xfree
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# ifndef XFree86LOADER
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# include <sys/mman.h>
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# endif
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#else
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# include <stdio.h>
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# include <stdlib.h>
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# include <unistd.h>
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# include <string.h>
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# include <ctype.h>
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# include <fcntl.h>
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# include <errno.h>
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# include <signal.h>
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# include <sys/types.h>
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# include <sys/ioctl.h>
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# include <sys/mman.h>
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# include <sys/time.h>
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# ifdef DRM_USE_MALLOC
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# define _DRM_MALLOC malloc
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# define _DRM_FREE free
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extern int xf86InstallSIGIOHandler(int fd, void (*f)(int, void *), void *);
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extern int xf86RemoveSIGIOHandler(int fd);
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# else
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# include <X11/Xlibint.h>
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# define _DRM_MALLOC Xmalloc
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# define _DRM_FREE Xfree
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# endif
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#endif
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/* Not all systems have MAP_FAILED defined */
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#ifndef MAP_FAILED
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#define MAP_FAILED ((void *)-1)
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#endif
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#ifdef __linux__
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#include <sys/sysmacros.h> /* for makedev() */
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#endif
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#include "xf86drm.h"
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#include "xf86drmCompat.h"
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#include "drm.h"
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#include "mga_drm.h"
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#include "r128_drm.h"
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#include "radeon_drm.h"
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2002-08-30 15:06:21 -06:00
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#ifndef __FreeBSD__
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2002-04-09 15:54:56 -06:00
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#include "sis_drm.h"
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2002-08-30 15:06:21 -06:00
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#include "i810_drm.h"
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2002-04-09 15:54:56 -06:00
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#include "i830_drm.h"
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2002-08-30 15:06:21 -06:00
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#endif
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2002-04-09 15:54:56 -06:00
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/* WARNING: Do not change, or add, anything to this file. It is only provided
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* for binary backwards compatability with the old driver specific DRM
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* extensions used before XFree86 4.3.
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*/
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2002-08-30 15:06:21 -06:00
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#ifndef __FreeBSD__
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2002-04-09 15:54:56 -06:00
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/* I810 */
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Bool drmI810CleanupDma(int driSubFD)
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{
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drm_i810_init_t init;
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memset(&init, 0, sizeof(drm_i810_init_t));
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init.func = I810_CLEANUP_DMA;
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if(ioctl(driSubFD, DRM_IOCTL_I810_INIT, &init)) {
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return 0; /* FALSE */
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}
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return 1; /* TRUE */
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}
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Bool drmI810InitDma(int driSubFD, drmCompatI810Init *info)
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{
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drm_i810_init_t init;
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memset(&init, 0, sizeof(drm_i810_init_t));
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init.func = I810_INIT_DMA;
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init.mmio_offset = info->mmio_offset;
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init.buffers_offset = info->buffers_offset;
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init.ring_start = info->start;
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init.ring_end = info->end;
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init.ring_size = info->size;
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init.sarea_priv_offset = info->sarea_off;
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init.front_offset = info->front_offset;
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init.back_offset = info->back_offset;
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init.depth_offset = info->depth_offset;
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init.overlay_offset = info->overlay_offset;
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init.overlay_physical = info->overlay_physical;
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init.w = info->w;
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init.h = info->h;
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init.pitch = info->pitch;
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init.pitch_bits = info->pitch_bits;
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if(ioctl(driSubFD, DRM_IOCTL_I810_INIT, &init)) {
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return 0; /* FALSE */
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}
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return 1; /* TRUE */
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}
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2002-08-30 15:06:21 -06:00
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#endif /* __FreeBSD__ */
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2002-04-09 15:54:56 -06:00
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/* Mga */
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#define MGA_IDLE_RETRY 2048
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int drmMGAInitDMA( int fd, drmCompatMGAInit *info )
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{
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drm_mga_init_t init;
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memset( &init, 0, sizeof(drm_mga_init_t) );
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init.func = MGA_INIT_DMA;
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init.sarea_priv_offset = info->sarea_priv_offset;
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init.sgram = info->sgram;
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init.chipset = info->chipset;
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init.maccess = info->maccess;
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init.fb_cpp = info->fb_cpp;
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init.front_offset = info->front_offset;
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init.front_pitch = info->front_pitch;
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init.back_offset = info->back_offset;
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init.back_pitch = info->back_pitch;
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init.depth_cpp = info->depth_cpp;
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init.depth_offset = info->depth_offset;
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init.depth_pitch = info->depth_pitch;
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init.texture_offset[0] = info->texture_offset[0];
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init.texture_size[0] = info->texture_size[0];
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init.texture_offset[1] = info->texture_offset[1];
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init.texture_size[1] = info->texture_size[1];
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init.fb_offset = info->fb_offset;
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init.mmio_offset = info->mmio_offset;
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init.status_offset = info->status_offset;
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init.warp_offset = info->warp_offset;
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init.primary_offset = info->primary_offset;
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init.buffers_offset = info->buffers_offset;
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if ( ioctl( fd, DRM_IOCTL_MGA_INIT, &init ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmMGACleanupDMA( int fd )
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{
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drm_mga_init_t init;
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memset( &init, 0, sizeof(drm_mga_init_t) );
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init.func = MGA_CLEANUP_DMA;
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if ( ioctl( fd, DRM_IOCTL_MGA_INIT, &init ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmMGAFlushDMA( int fd, drmLockFlags flags )
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{
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drm_lock_t lock;
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int ret, i = 0;
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memset( &lock, 0, sizeof(drm_lock_t) );
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if ( flags & DRM_LOCK_QUIESCENT ) lock.flags |= _DRM_LOCK_QUIESCENT;
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if ( flags & DRM_LOCK_FLUSH ) lock.flags |= _DRM_LOCK_FLUSH;
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if ( flags & DRM_LOCK_FLUSH_ALL ) lock.flags |= _DRM_LOCK_FLUSH_ALL;
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do {
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ret = ioctl( fd, DRM_IOCTL_MGA_FLUSH, &lock );
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} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
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if ( ret == 0 )
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return 0;
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if ( errno != EBUSY )
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return -errno;
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if ( lock.flags & _DRM_LOCK_QUIESCENT ) {
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/* Only keep trying if we need quiescence.
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*/
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lock.flags &= ~(_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL);
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do {
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ret = ioctl( fd, DRM_IOCTL_MGA_FLUSH, &lock );
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} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
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}
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if ( ret == 0 ) {
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return 0;
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} else {
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return -errno;
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}
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}
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int drmMGAEngineReset( int fd )
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{
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if ( ioctl( fd, DRM_IOCTL_MGA_RESET, NULL ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmMGAFullScreen( int fd, int enable )
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{
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return -EINVAL;
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}
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int drmMGASwapBuffers( int fd )
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{
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int ret, i = 0;
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do {
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ret = ioctl( fd, DRM_IOCTL_MGA_SWAP, NULL );
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} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
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if ( ret == 0 ) {
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return 0;
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} else {
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return -errno;
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}
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}
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int drmMGAClear( int fd, unsigned int flags,
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unsigned int clear_color, unsigned int clear_depth,
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unsigned int color_mask, unsigned int depth_mask )
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{
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drm_mga_clear_t clear;
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int ret, i = 0;
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clear.flags = flags;
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clear.clear_color = clear_color;
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clear.clear_depth = clear_depth;
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clear.color_mask = color_mask;
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clear.depth_mask = depth_mask;
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do {
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ret = ioctl( fd, DRM_IOCTL_MGA_CLEAR, &clear );
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} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
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if ( ret == 0 ) {
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return 0;
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} else {
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return -errno;
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}
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}
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int drmMGAFlushVertexBuffer( int fd, int index, int used, int discard )
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{
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drm_mga_vertex_t vertex;
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vertex.idx = index;
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vertex.used = used;
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vertex.discard = discard;
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if ( ioctl( fd, DRM_IOCTL_MGA_VERTEX, &vertex ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmMGAFlushIndices( int fd, int index, int start, int end, int discard )
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{
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drm_mga_indices_t indices;
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indices.idx = index;
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indices.start = start;
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indices.end = end;
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indices.discard = discard;
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if ( ioctl( fd, DRM_IOCTL_MGA_INDICES, &indices ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmMGATextureLoad( int fd, int index,
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|
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unsigned int dstorg, unsigned int length )
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{
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|
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drm_mga_iload_t iload;
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int ret, i = 0;
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iload.idx = index;
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iload.dstorg = dstorg;
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iload.length = length;
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do {
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ret = ioctl( fd, DRM_IOCTL_MGA_ILOAD, &iload );
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} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
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if ( ret == 0 ) {
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|
return 0;
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} else {
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return -errno;
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}
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}
|
|
|
|
|
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|
|
int drmMGAAgpBlit( int fd, unsigned int planemask,
|
|
|
|
unsigned int src_offset, int src_pitch,
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|
|
unsigned int dst_offset, int dst_pitch,
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|
|
int delta_sx, int delta_sy,
|
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|
|
int delta_dx, int delta_dy,
|
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|
|
int height, int ydir )
|
|
|
|
{
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|
|
drm_mga_blit_t blit;
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|
|
int ret, i = 0;
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|
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blit.planemask = planemask;
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|
|
blit.srcorg = src_offset;
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|
|
blit.dstorg = dst_offset;
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|
|
blit.src_pitch = src_pitch;
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|
blit.dst_pitch = dst_pitch;
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|
|
blit.delta_sx = delta_sx;
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blit.delta_sy = delta_sy;
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|
blit.delta_dx = delta_dx;
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blit.delta_dx = delta_dx;
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|
|
blit.height = height;
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|
|
blit.ydir = ydir;
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|
|
do {
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|
|
ret = ioctl( fd, DRM_IOCTL_MGA_BLIT, &blit );
|
|
|
|
} while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY );
|
|
|
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|
|
|
if ( ret == 0 ) {
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
return -errno;
|
|
|
|
}
|
|
|
|
}
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/* R128 */
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#define R128_BUFFER_RETRY 32
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#define R128_IDLE_RETRY 32
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int drmR128InitCCE( int fd, drmCompatR128Init *info )
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{
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drm_r128_init_t init;
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memset( &init, 0, sizeof(drm_r128_init_t) );
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init.func = R128_INIT_CCE;
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init.sarea_priv_offset = info->sarea_priv_offset;
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init.is_pci = info->is_pci;
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init.cce_mode = info->cce_mode;
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init.cce_secure = info->cce_secure;
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init.ring_size = info->ring_size;
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init.usec_timeout = info->usec_timeout;
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init.fb_bpp = info->fb_bpp;
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init.front_offset = info->front_offset;
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init.front_pitch = info->front_pitch;
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init.back_offset = info->back_offset;
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init.back_pitch = info->back_pitch;
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init.depth_bpp = info->depth_bpp;
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init.depth_offset = info->depth_offset;
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init.depth_pitch = info->depth_pitch;
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init.span_offset = info->span_offset;
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init.fb_offset = info->fb_offset;
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init.mmio_offset = info->mmio_offset;
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init.ring_offset = info->ring_offset;
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init.ring_rptr_offset = info->ring_rptr_offset;
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init.buffers_offset = info->buffers_offset;
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init.agp_textures_offset = info->agp_textures_offset;
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if ( ioctl( fd, DRM_IOCTL_R128_INIT, &init ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128CleanupCCE( int fd )
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{
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drm_r128_init_t init;
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memset( &init, 0, sizeof(drm_r128_init_t) );
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init.func = R128_CLEANUP_CCE;
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if ( ioctl( fd, DRM_IOCTL_R128_INIT, &init ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128StartCCE( int fd )
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{
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if ( ioctl( fd, DRM_IOCTL_R128_CCE_START, NULL ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128StopCCE( int fd )
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{
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drm_r128_cce_stop_t stop;
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int ret, i = 0;
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stop.flush = 1;
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stop.idle = 1;
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ret = ioctl( fd, DRM_IOCTL_R128_CCE_STOP, &stop );
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if ( ret == 0 ) {
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return 0;
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} else if ( errno != EBUSY ) {
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return -errno;
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}
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stop.flush = 0;
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do {
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ret = ioctl( fd, DRM_IOCTL_R128_CCE_STOP, &stop );
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} while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY );
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if ( ret == 0 ) {
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return 0;
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} else if ( errno != EBUSY ) {
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return -errno;
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}
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stop.idle = 0;
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if ( ioctl( fd, DRM_IOCTL_R128_CCE_STOP, &stop ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128ResetCCE( int fd )
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{
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if ( ioctl( fd, DRM_IOCTL_R128_CCE_RESET, NULL ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128WaitForIdleCCE( int fd )
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{
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int ret, i = 0;
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do {
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ret = ioctl( fd, DRM_IOCTL_R128_CCE_IDLE, NULL );
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} while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY );
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if ( ret == 0 ) {
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return 0;
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} else {
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return -errno;
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}
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}
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int drmR128EngineReset( int fd )
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{
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if ( ioctl( fd, DRM_IOCTL_R128_RESET, NULL ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128FullScreen( int fd, int enable )
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{
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drm_r128_fullscreen_t fs;
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if ( enable ) {
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fs.func = R128_INIT_FULLSCREEN;
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} else {
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fs.func = R128_CLEANUP_FULLSCREEN;
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}
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if ( ioctl( fd, DRM_IOCTL_R128_FULLSCREEN, &fs ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128SwapBuffers( int fd )
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{
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if ( ioctl( fd, DRM_IOCTL_R128_SWAP, NULL ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128Clear( int fd, unsigned int flags,
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unsigned int clear_color, unsigned int clear_depth,
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unsigned int color_mask, unsigned int depth_mask )
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{
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drm_r128_clear_t clear;
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clear.flags = flags;
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clear.clear_color = clear_color;
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clear.clear_depth = clear_depth;
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clear.color_mask = color_mask;
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clear.depth_mask = depth_mask;
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if ( ioctl( fd, DRM_IOCTL_R128_CLEAR, &clear ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128FlushVertexBuffer( int fd, int prim, int index,
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int count, int discard )
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{
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drm_r128_vertex_t v;
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v.prim = prim;
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v.idx = index;
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v.count = count;
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v.discard = discard;
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if ( ioctl( fd, DRM_IOCTL_R128_VERTEX, &v ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128FlushIndices( int fd, int prim, int index,
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int start, int end, int discard )
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{
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drm_r128_indices_t elts;
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elts.prim = prim;
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elts.idx = index;
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elts.start = start;
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elts.end = end;
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elts.discard = discard;
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if ( ioctl( fd, DRM_IOCTL_R128_INDICES, &elts ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128TextureBlit( int fd, int index,
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int offset, int pitch, int format,
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int x, int y, int width, int height )
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{
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drm_r128_blit_t blit;
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blit.idx = index;
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blit.offset = offset;
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blit.pitch = pitch;
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blit.format = format;
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blit.x = x;
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blit.y = y;
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blit.width = width;
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blit.height = height;
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if ( ioctl( fd, DRM_IOCTL_R128_BLIT, &blit ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128WriteDepthSpan( int fd, int n, int x, int y,
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const unsigned int depth[],
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const unsigned char mask[] )
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{
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drm_r128_depth_t d;
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d.func = R128_WRITE_SPAN;
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d.n = n;
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d.x = &x;
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d.y = &y;
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d.buffer = (unsigned int *)depth;
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d.mask = (unsigned char *)mask;
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if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128WriteDepthPixels( int fd, int n,
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const int x[], const int y[],
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const unsigned int depth[],
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const unsigned char mask[] )
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{
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drm_r128_depth_t d;
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d.func = R128_WRITE_PIXELS;
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d.n = n;
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d.x = (int *)x;
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d.y = (int *)y;
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d.buffer = (unsigned int *)depth;
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d.mask = (unsigned char *)mask;
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if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128ReadDepthSpan( int fd, int n, int x, int y )
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{
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drm_r128_depth_t d;
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d.func = R128_READ_SPAN;
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d.n = n;
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d.x = &x;
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d.y = &y;
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d.buffer = NULL;
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d.mask = NULL;
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if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128ReadDepthPixels( int fd, int n,
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const int x[], const int y[] )
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{
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drm_r128_depth_t d;
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d.func = R128_READ_PIXELS;
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d.n = n;
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d.x = (int *)x;
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d.y = (int *)y;
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d.buffer = NULL;
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d.mask = NULL;
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if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128PolygonStipple( int fd, unsigned int *mask )
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{
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drm_r128_stipple_t stipple;
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stipple.mask = mask;
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if ( ioctl( fd, DRM_IOCTL_R128_STIPPLE, &stipple ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmR128FlushIndirectBuffer( int fd, int index,
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int start, int end, int discard )
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{
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drm_r128_indirect_t ind;
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ind.idx = index;
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ind.start = start;
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ind.end = end;
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ind.discard = discard;
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if ( ioctl( fd, DRM_IOCTL_R128_INDIRECT, &ind ) < 0 ) {
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return -errno;
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} else {
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|
return 0;
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}
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|
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}
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|
|
|
|
|
|
/* Radeon */
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|
|
|
|
|
|
#define RADEON_BUFFER_RETRY 32
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|
|
#define RADEON_IDLE_RETRY 16
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|
|
|
|
|
|
int drmRadeonInitCP( int fd, drmCompatRadeonInit *info )
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|
|
{
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|
|
drm_radeon_init_t init;
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|
|
|
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|
|
memset( &init, 0, sizeof(drm_radeon_init_t) );
|
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|
|
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|
|
init.func = RADEON_INIT_CP;
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|
|
init.sarea_priv_offset = info->sarea_priv_offset;
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|
|
init.is_pci = info->is_pci;
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|
|
init.cp_mode = info->cp_mode;
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|
|
init.agp_size = info->agp_size;
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|
|
init.ring_size = info->ring_size;
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|
|
init.usec_timeout = info->usec_timeout;
|
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|
|
|
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|
|
init.fb_bpp = info->fb_bpp;
|
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|
|
init.front_offset = info->front_offset;
|
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|
|
init.front_pitch = info->front_pitch;
|
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|
|
init.back_offset = info->back_offset;
|
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|
|
init.back_pitch = info->back_pitch;
|
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|
|
|
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|
|
init.depth_bpp = info->depth_bpp;
|
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|
|
init.depth_offset = info->depth_offset;
|
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|
|
init.depth_pitch = info->depth_pitch;
|
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|
|
|
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|
|
init.fb_offset = info->fb_offset;
|
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|
|
init.mmio_offset = info->mmio_offset;
|
|
|
|
init.ring_offset = info->ring_offset;
|
|
|
|
init.ring_rptr_offset = info->ring_rptr_offset;
|
|
|
|
init.buffers_offset = info->buffers_offset;
|
|
|
|
init.agp_textures_offset = info->agp_textures_offset;
|
|
|
|
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_CP_INIT, &init ) ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonCleanupCP( int fd )
|
|
|
|
{
|
|
|
|
drm_radeon_init_t init;
|
|
|
|
|
|
|
|
memset( &init, 0, sizeof(drm_radeon_init_t) );
|
|
|
|
|
|
|
|
init.func = RADEON_CLEANUP_CP;
|
|
|
|
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_CP_INIT, &init ) ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonStartCP( int fd )
|
|
|
|
{
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_CP_START, NULL ) ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonStopCP( int fd )
|
|
|
|
{
|
|
|
|
drm_radeon_cp_stop_t stop;
|
|
|
|
int ret, i = 0;
|
|
|
|
|
|
|
|
stop.flush = 1;
|
|
|
|
stop.idle = 1;
|
|
|
|
|
|
|
|
ret = ioctl( fd, DRM_IOCTL_RADEON_CP_STOP, &stop );
|
|
|
|
|
|
|
|
if ( ret == 0 ) {
|
|
|
|
return 0;
|
|
|
|
} else if ( errno != EBUSY ) {
|
|
|
|
return -errno;
|
|
|
|
}
|
|
|
|
|
|
|
|
stop.flush = 0;
|
|
|
|
|
|
|
|
do {
|
|
|
|
ret = ioctl( fd, DRM_IOCTL_RADEON_CP_STOP, &stop );
|
|
|
|
} while ( ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY );
|
|
|
|
|
|
|
|
if ( ret == 0 ) {
|
|
|
|
return 0;
|
|
|
|
} else if ( errno != EBUSY ) {
|
|
|
|
return -errno;
|
|
|
|
}
|
|
|
|
|
|
|
|
stop.idle = 0;
|
|
|
|
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_CP_STOP, &stop ) ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonResetCP( int fd )
|
|
|
|
{
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_CP_RESET, NULL ) ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonWaitForIdleCP( int fd )
|
|
|
|
{
|
|
|
|
int ret, i = 0;
|
|
|
|
|
|
|
|
do {
|
|
|
|
ret = ioctl( fd, DRM_IOCTL_RADEON_CP_IDLE, NULL );
|
|
|
|
} while ( ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY );
|
|
|
|
|
|
|
|
if ( ret == 0 ) {
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
return -errno;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonEngineReset( int fd )
|
|
|
|
{
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_RESET, NULL ) ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonFullScreen( int fd, int enable )
|
|
|
|
{
|
|
|
|
drm_radeon_fullscreen_t fs;
|
|
|
|
|
|
|
|
if ( enable ) {
|
|
|
|
fs.func = RADEON_INIT_FULLSCREEN;
|
|
|
|
} else {
|
|
|
|
fs.func = RADEON_CLEANUP_FULLSCREEN;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_FULLSCREEN, &fs ) ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonSwapBuffers( int fd )
|
|
|
|
{
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_SWAP, NULL ) ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonClear( int fd, unsigned int flags,
|
|
|
|
unsigned int clear_color, unsigned int clear_depth,
|
|
|
|
unsigned int color_mask, unsigned int stencil,
|
|
|
|
void *b, int nbox )
|
|
|
|
{
|
|
|
|
drm_radeon_clear_t clear;
|
|
|
|
drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
|
|
|
|
drm_clip_rect_t *boxes = (drm_clip_rect_t *)b;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
clear.flags = flags;
|
|
|
|
clear.clear_color = clear_color;
|
|
|
|
clear.clear_depth = clear_depth;
|
|
|
|
clear.color_mask = color_mask;
|
|
|
|
clear.depth_mask = stencil; /* misnamed field in ioctl */
|
|
|
|
clear.depth_boxes = depth_boxes;
|
|
|
|
|
|
|
|
/* We can remove this when we do real depth clears, instead of
|
|
|
|
* rendering a rectangle into the depth buffer. This prevents
|
|
|
|
* floating point calculations being done in the kernel.
|
|
|
|
*/
|
|
|
|
for ( i = 0 ; i < nbox ; i++ ) {
|
|
|
|
depth_boxes[i].f[CLEAR_X1] = (float)boxes[i].x1;
|
|
|
|
depth_boxes[i].f[CLEAR_Y1] = (float)boxes[i].y1;
|
|
|
|
depth_boxes[i].f[CLEAR_X2] = (float)boxes[i].x2;
|
|
|
|
depth_boxes[i].f[CLEAR_Y2] = (float)boxes[i].y2;
|
|
|
|
depth_boxes[i].f[CLEAR_DEPTH] = (float)clear_depth;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_CLEAR, &clear ) < 0 ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonFlushVertexBuffer( int fd, int prim, int index,
|
|
|
|
int count, int discard )
|
|
|
|
{
|
|
|
|
drm_radeon_vertex_t v;
|
|
|
|
|
|
|
|
v.prim = prim;
|
|
|
|
v.idx = index;
|
|
|
|
v.count = count;
|
|
|
|
v.discard = discard;
|
|
|
|
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_VERTEX, &v ) < 0 ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonFlushIndices( int fd, int prim, int index,
|
|
|
|
int start, int end, int discard )
|
|
|
|
{
|
|
|
|
drm_radeon_indices_t elts;
|
|
|
|
|
|
|
|
elts.prim = prim;
|
|
|
|
elts.idx = index;
|
|
|
|
elts.start = start;
|
|
|
|
elts.end = end;
|
|
|
|
elts.discard = discard;
|
|
|
|
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_INDICES, &elts ) < 0 ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonLoadTexture( int fd, int offset, int pitch, int format, int width,
|
|
|
|
int height, drmCompatRadeonTexImage *image )
|
|
|
|
{
|
|
|
|
drm_radeon_texture_t tex;
|
|
|
|
drm_radeon_tex_image_t tmp;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
tex.offset = offset;
|
|
|
|
tex.pitch = pitch;
|
|
|
|
tex.format = format;
|
|
|
|
tex.width = width;
|
|
|
|
tex.height = height;
|
|
|
|
tex.image = &tmp;
|
|
|
|
|
|
|
|
/* This gets updated by the kernel when a multipass blit is needed.
|
|
|
|
*/
|
|
|
|
memcpy( &tmp, image, sizeof(drm_radeon_tex_image_t) );
|
|
|
|
|
|
|
|
do {
|
|
|
|
ret = ioctl( fd, DRM_IOCTL_RADEON_TEXTURE, &tex );
|
|
|
|
} while ( ret && errno == EAGAIN );
|
|
|
|
|
|
|
|
if ( ret == 0 ) {
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
return -errno;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonPolygonStipple( int fd, unsigned int *mask )
|
|
|
|
{
|
|
|
|
drm_radeon_stipple_t stipple;
|
|
|
|
|
|
|
|
stipple.mask = mask;
|
|
|
|
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_STIPPLE, &stipple ) < 0 ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int drmRadeonFlushIndirectBuffer( int fd, int index,
|
|
|
|
int start, int end, int discard )
|
|
|
|
{
|
|
|
|
drm_radeon_indirect_t ind;
|
|
|
|
|
|
|
|
ind.idx = index;
|
|
|
|
ind.start = start;
|
|
|
|
ind.end = end;
|
|
|
|
ind.discard = discard;
|
|
|
|
|
|
|
|
if ( ioctl( fd, DRM_IOCTL_RADEON_INDIRECT, &ind ) < 0 ) {
|
|
|
|
return -errno;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2002-08-30 15:06:21 -06:00
|
|
|
#ifndef __FreeBSD__
|
2002-04-09 15:54:56 -06:00
|
|
|
/* SiS */
|
|
|
|
|
|
|
|
Bool drmSiSAgpInit(int driSubFD, int offset, int size)
|
|
|
|
{
|
|
|
|
drm_sis_agp_t agp;
|
|
|
|
|
|
|
|
agp.offset = offset;
|
|
|
|
agp.size = size;
|
|
|
|
ioctl(driSubFD, SIS_IOCTL_AGP_INIT, &agp);
|
|
|
|
|
|
|
|
return 1; /* TRUE */
|
|
|
|
}
|
|
|
|
|
|
|
|
/* I830 */
|
|
|
|
|
|
|
|
Bool drmI830CleanupDma(int driSubFD)
|
|
|
|
{
|
|
|
|
drm_i830_init_t init;
|
|
|
|
|
|
|
|
memset(&init, 0, sizeof(drm_i830_init_t));
|
|
|
|
init.func = I810_CLEANUP_DMA;
|
|
|
|
|
|
|
|
if(ioctl(driSubFD, DRM_IOCTL_I830_INIT, &init)) {
|
|
|
|
return 0; /* FALSE */
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1; /* TRUE */
|
|
|
|
}
|
|
|
|
|
|
|
|
Bool drmI830InitDma(int driSubFD, drmCompatI830Init *info)
|
|
|
|
{
|
|
|
|
drm_i830_init_t init;
|
|
|
|
|
|
|
|
memset(&init, 0, sizeof(drm_i830_init_t));
|
|
|
|
|
|
|
|
init.func = I810_INIT_DMA;
|
|
|
|
init.mmio_offset = info->mmio_offset;
|
|
|
|
init.buffers_offset = info->buffers_offset;
|
|
|
|
init.ring_start = info->start;
|
|
|
|
init.ring_end = info->end;
|
|
|
|
init.ring_size = info->size;
|
|
|
|
init.sarea_priv_offset = info->sarea_off;
|
|
|
|
init.front_offset = info->front_offset;
|
|
|
|
init.back_offset = info->back_offset;
|
|
|
|
init.depth_offset = info->depth_offset;
|
|
|
|
init.w = info->w;
|
|
|
|
init.h = info->h;
|
|
|
|
init.pitch = info->pitch;
|
|
|
|
init.pitch_bits = info->pitch_bits;
|
|
|
|
init.back_pitch = info->pitch;
|
|
|
|
init.depth_pitch = info->pitch;
|
|
|
|
init.cpp = info->cpp;
|
|
|
|
|
|
|
|
if(ioctl(driSubFD, DRM_IOCTL_I830_INIT, &init)) {
|
|
|
|
return 0; /* FALSE */
|
|
|
|
}
|
|
|
|
return 1; /* TRUE */
|
|
|
|
}
|
2002-08-30 15:06:21 -06:00
|
|
|
#endif /* __FreeBSD__ */
|
2002-04-09 15:54:56 -06:00
|
|
|
|
|
|
|
/* WARNING: Do not change, or add, anything to this file. It is only provided
|
|
|
|
* for binary backwards compatability with the old driver specific DRM
|
|
|
|
* extensions used before XFree86 4.3.
|
|
|
|
*/
|