118 lines
3.3 KiB
C
118 lines
3.3 KiB
C
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/**************************************************************************
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*
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* Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*
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**************************************************************************/
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/*
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* Authors: Thomas Hellstr<EFBFBD>m <thomas-at-tungstengraphics-dot-com>
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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drm_ttm_backend_t *radeon_create_ttm_backend_entry(drm_device_t * dev)
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{
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return drm_agp_init_ttm(dev, NULL);
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}
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int radeon_fence_types(drm_buffer_object_t *bo, uint32_t * class, uint32_t * type)
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{
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*class = 0;
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if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE))
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*type = 3;
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else
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*type = 1;
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return 0;
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}
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int radeon_invalidate_caches(drm_device_t * dev, uint32_t flags)
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{
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/*
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* FIXME: Only emit once per batchbuffer submission.
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*/
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#if 0
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uint32_t flush_cmd = MI_NO_WRITE_FLUSH;
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if (flags & DRM_BO_FLAG_READ)
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flush_cmd |= MI_READ_FLUSH;
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if (flags & DRM_BO_FLAG_EXE)
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flush_cmd |= MI_EXE_FLUSH;
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return 0;
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// return radeon_emit_mi_flush(dev, flush_cmd);
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#endif
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return 0;
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}
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uint32_t radeon_evict_mask(drm_buffer_object_t *bo)
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{
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switch (bo->mem.mem_type) {
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case DRM_BO_MEM_LOCAL:
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case DRM_BO_MEM_TT:
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return DRM_BO_FLAG_MEM_LOCAL;
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default:
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return DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_CACHED;
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}
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}
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int radeon_init_mem_type(drm_device_t * dev, uint32_t type,
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drm_mem_type_manager_t * man)
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{
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switch (type) {
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case DRM_BO_MEM_LOCAL:
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man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
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_DRM_FLAG_MEMTYPE_CACHED;
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man->drm_bus_maptype = 0;
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break;
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case DRM_BO_MEM_TT:
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if (!(drm_core_has_AGP(dev) && dev->agp)) {
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DRM_ERROR("AGP is not enabled for memory type %u\n",
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(unsigned)type);
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return -EINVAL;
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}
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man->io_offset = dev->agp->agp_info.aper_base;
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man->io_size = dev->agp->agp_info.aper_size * 1024 * 1024;
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man->io_addr = NULL;
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man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
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_DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_NEEDS_IOREMAP;
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man->drm_bus_maptype = _DRM_AGP;
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break;
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default:
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DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
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return -EINVAL;
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}
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return 0;
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}
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int radeon_move(drm_buffer_object_t * bo,
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int evict, int no_wait, drm_bo_mem_reg_t * new_mem)
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{
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return 0;
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}
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