244 lines
7.3 KiB
C
244 lines
7.3 KiB
C
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/*
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* Based on nv40_graph.c
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* Someday this will all go away...
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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/*
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* TODO: In the dump start seems to be 7654b0 while end is 76ac28.
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* This is obviously not the correct size.
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*/
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#define NV30_GRCTX_SIZE (22392)
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/*TODO: deciper what each offset in the context represents. The below
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* contexts are taken from dumps just after the 3D object is
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* created.
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*/
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static void nv30_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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int i;
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INSTANCE_WR(ctx, 0x28/4, 0x10000000);
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INSTANCE_WR(ctx, 0x40c/4, 0x00000101);
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INSTANCE_WR(ctx, 0x420/4, 0x00000111);
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INSTANCE_WR(ctx, 0x424/4, 0x00000060);
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INSTANCE_WR(ctx, 0x440/4, 0x00000080);
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INSTANCE_WR(ctx, 0x444/4, 0xffff0000);
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INSTANCE_WR(ctx, 0x448/4, 0x00000001);
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INSTANCE_WR(ctx, 0x45c/4, 0x44400000);
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INSTANCE_WR(ctx, 0x448/4, 0xffff0000);
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INSTANCE_WR(ctx, 0x4dc/4, 0xfff00000);
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INSTANCE_WR(ctx, 0x4e0/4, 0xfff00000);
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INSTANCE_WR(ctx, 0x4e8/4, 0x00011100);
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for (i = 0x504; i <= 0x540; i += 4)
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INSTANCE_WR(ctx, i/4, 0x7ff00000);
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INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff);
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INSTANCE_WR(ctx, 0x588/4, 0x00000080);
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INSTANCE_WR(ctx, 0x58c/4, 0x30201000);
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INSTANCE_WR(ctx, 0x590/4, 0x70605040);
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INSTANCE_WR(ctx, 0x594/4, 0xb8a89888);
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INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8);
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INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000);
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for (i = 0x604; i <= 0x640; i += 4)
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INSTANCE_WR(ctx, i/4, 0x00010588);
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for (i = 0x644; i <= 0x680; i += 4)
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INSTANCE_WR(ctx, i/4, 0x00030303);
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for (i = 0x6c4; i <= 0x700; i += 4)
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INSTANCE_WR(ctx, i/4, 0x0008aae4);
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for (i = 0x704; i <= 0x740; i += 4)
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INSTANCE_WR(ctx, i/4, 0x1012000);
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for (i = 0x744; i <= 0x780; i += 4)
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INSTANCE_WR(ctx, i/4, 0x0080008);
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INSTANCE_WR(ctx, 0x860/4, 0x00040000);
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INSTANCE_WR(ctx, 0x864/4, 0x00010000);
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INSTANCE_WR(ctx, 0x868/4, 0x00040000);
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INSTANCE_WR(ctx, 0x86c/4, 0x00040000);
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INSTANCE_WR(ctx, 0x870/4, 0x00040000);
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INSTANCE_WR(ctx, 0x874/4, 0x00040000);
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for (i = 0x00; i <= 0x1170; i += 0x10)
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{
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INSTANCE_WR(ctx, (0x1f24 + i)/4, 0x000c001b);
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INSTANCE_WR(ctx, (0x1f20 + i)/4, 0x0436086c);
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INSTANCE_WR(ctx, (0x1f1c + i)/4, 0x10700ff9);
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}
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INSTANCE_WR(ctx, 0x30bc/4, 0x0000ffff);
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INSTANCE_WR(ctx, 0x30c0/4, 0x0000ffff);
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INSTANCE_WR(ctx, 0x30c4/4, 0x0000ffff);
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INSTANCE_WR(ctx, 0x30c8/4, 0x0000ffff);
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INSTANCE_WR(ctx, 0x380c/4, 0x3f800000);
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INSTANCE_WR(ctx, 0x3450/4, 0x3f800000);
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INSTANCE_WR(ctx, 0x3820/4, 0x3f800000);
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INSTANCE_WR(ctx, 0x3854/4, 0x3f800000);
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INSTANCE_WR(ctx, 0x3850/4, 0x3f000000);
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INSTANCE_WR(ctx, 0x384c/4, 0x40000000);
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INSTANCE_WR(ctx, 0x3868/4, 0xbf800000);
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INSTANCE_WR(ctx, 0x3860/4, 0x3f800000);
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INSTANCE_WR(ctx, 0x386c/4, 0x40000000);
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INSTANCE_WR(ctx, 0x3870/4, 0xbf800000);
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for (i = 0x4e0; i <= 0x4e1c; i += 4)
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INSTANCE_WR(ctx, i/4, 0x001c527d);
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INSTANCE_WR(ctx, 0x4e40, 0x001c527c);
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INSTANCE_WR(ctx, 0x5680/4, 0x000a0000);
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INSTANCE_WR(ctx, 0x87c/4, 0x10000000);
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INSTANCE_WR(ctx, 0x28/4, 0x10000011);
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}
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int
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nv30_graph_context_create(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv =
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(drm_nouveau_private_t *)dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[channel];
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void (*ctx_init)(drm_device_t *, struct mem_block *);
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unsigned int ctx_size;
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int i, chipset;
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chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
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switch (chipset) {
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default:
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ctx_size = NV30_GRCTX_SIZE;
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ctx_init = nv30_graph_context_init;
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break;
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}
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/* Alloc and clear RAMIN to store the context */
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chan->ramin_grctx = nouveau_instmem_alloc(dev, ctx_size, 4);
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if (!chan->ramin_grctx)
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return DRM_ERR(ENOMEM);
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for (i=0; i<ctx_size; i+=4)
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INSTANCE_WR(chan->ramin_grctx, i/4, 0x00000000);
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/* Initialise default context values */
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ctx_init(dev, chan->ramin_grctx);
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return 0;
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}
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#if 0
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/* Save current context (from PGRAPH) into the channel's context
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*XXX: fails sometimes, not sure why..
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*/
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void
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nv40_graph_context_save_current(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv =
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(drm_nouveau_private_t *)dev->dev_private;
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uint32_t instance;
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int i;
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NV_WRITE(NV_PGRAPH_FIFO, 0);
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instance = NV_READ(0x40032C) & 0xFFFFF;
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if (!instance) {
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NV_WRITE(NV_PGRAPH_FIFO, 1);
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return;
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}
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NV_WRITE(0x400784, instance);
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NV_WRITE(0x400310, NV_READ(0x400310) | 0x20);
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NV_WRITE(0x400304, 1);
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/* just in case, we don't want to spin in-kernel forever */
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for (i=0; i<1000; i++) {
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if (NV_READ(0x40030C) == 0)
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break;
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}
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if (i==1000) {
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DRM_ERROR("failed to save current grctx to ramin\n");
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DRM_ERROR("instance = 0x%08x\n", NV_READ(0x40032C));
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DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
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NV_WRITE(NV_PGRAPH_FIFO, 1);
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return;
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}
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NV_WRITE(NV_PGRAPH_FIFO, 1);
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}
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/* Restore the context for a specific channel into PGRAPH
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* XXX: fails sometimes.. not sure why
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*/
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void
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nv40_graph_context_restore(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv =
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(drm_nouveau_private_t *)dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[channel];
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uint32_t instance;
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int i;
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instance = nouveau_chip_instance_get(dev, chan->ramin_grctx);
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NV_WRITE(NV_PGRAPH_FIFO, 0);
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NV_WRITE(0x400784, instance);
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NV_WRITE(0x400310, NV_READ(0x400310) | 0x40);
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NV_WRITE(0x400304, 1);
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/* just in case, we don't want to spin in-kernel forever */
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for (i=0; i<1000; i++) {
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if (NV_READ(0x40030C) == 0)
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break;
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}
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if (i==1000) {
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DRM_ERROR("failed to restore grctx for ch%d to PGRAPH\n",
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channel);
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DRM_ERROR("instance = 0x%08x\n", instance);
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DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
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NV_WRITE(NV_PGRAPH_FIFO, 1);
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return;
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}
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/* 0x40032C, no idea of it's exact function. Could simply be a
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* record of the currently active PGRAPH context. It's currently
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* unknown as to what bit 24 does. The nv ddx has it set, so we will
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* set it here too.
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*/
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NV_WRITE(0x40032C, instance | 0x01000000);
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/* 0x32E0 records the instance address of the active FIFO's PGRAPH
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* context. If at any time this doesn't match 0x40032C, you will
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* recieve PGRAPH_INTR_CONTEXT_SWITCH
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*/
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NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, instance);
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NV_WRITE(NV_PGRAPH_FIFO, 1);
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}
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#endif
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int
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nv30_graph_init(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv =
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(drm_nouveau_private_t *)dev->dev_private;
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int i, chipset;
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chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
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DRM_DEBUG("chipset (from PMC_BOOT_0): NV%02X\n", chipset);
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/* Create Context Pointer Table */
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dev_priv->ctx_table_size = 32 * 4;
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dev_priv->ctx_table = nouveau_instmem_alloc(dev, dev_priv->ctx_table_size, 4);
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if (!dev_priv->ctx_table)
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return DRM_ERR(ENOMEM);
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for (i=0; i< dev_priv->ctx_table_size; i+=4)
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INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000);
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NV_WRITE(NV_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
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return 0;
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}
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