Use DRM_READ/DRM_WRITE macros instead of directly accessing MMIO space.
Ian Romanick
parent
2ac80e79e4
commit
01628a430d
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@ -27,6 +27,8 @@
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#include "xgi_drv.h"
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#include "xgi_regs.h"
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#include <linux/delay.h>
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int xgi_ge_reset_ioctl(struct drm_device * dev, void * data,
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struct drm_file * filp)
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{
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@ -46,47 +48,43 @@ int xgi_ge_reset_ioctl(struct drm_device * dev, void * data,
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static unsigned int s_invalid_begin = 0;
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static bool xgi_validate_signal(volatile u8 *mmio_vbase)
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static bool xgi_validate_signal(struct drm_map * map)
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{
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volatile u32 *const ge_3d_status =
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(volatile u32 *)(mmio_vbase + 0x2800);
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const u32 old_ge_status = ge_3d_status[0x00];
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if (old_ge_status & 0x001c0000) {
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if (DRM_READ32(map, 0x2800) & 0x001c0000) {
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u16 check;
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/* Check Read back status */
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*(mmio_vbase + 0x235c) = 0x80;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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DRM_WRITE8(map, 0x235c, 0x80);
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check = DRM_READ16(map, 0x2360);
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if ((check & 0x3f) != ((check & 0x3f00) >> 8)) {
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return FALSE;
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}
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/* Check RO channel */
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*(mmio_vbase + 0x235c) = 0x83;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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DRM_WRITE8(map, 0x235c, 0x83);
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check = DRM_READ16(map, 0x2360);
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if ((check & 0x0f) != ((check & 0xf0) >> 4)) {
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return FALSE;
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}
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/* Check RW channel */
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*(mmio_vbase + 0x235c) = 0x88;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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DRM_WRITE8(map, 0x235c, 0x88);
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check = DRM_READ16(map, 0x2360);
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if ((check & 0x0f) != ((check & 0xf0) >> 4)) {
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return FALSE;
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}
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/* Check RO channel outstanding */
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*(mmio_vbase + 0x235c) = 0x8f;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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DRM_WRITE8(map, 0x235c, 0x8f);
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check = DRM_READ16(map, 0x2360);
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if (0 != (check & 0x3ff)) {
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return FALSE;
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}
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/* Check RW channel outstanding */
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*(mmio_vbase + 0x235c) = 0x90;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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DRM_WRITE8(map, 0x235c, 0x90);
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check = DRM_READ16(map, 0x2360);
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if (0 != (check & 0x3ff)) {
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return FALSE;
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}
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@ -98,14 +96,12 @@ static bool xgi_validate_signal(volatile u8 *mmio_vbase)
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}
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static void xgi_ge_hang_reset(volatile u8 *mmio_vbase)
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static void xgi_ge_hang_reset(struct drm_map * map)
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{
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volatile u32 *const ge_3d_status =
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(volatile u32 *)(mmio_vbase + 0x2800);
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int time_out = 0xffff;
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*(mmio_vbase + 0xb057) = 8;
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while (0 != (ge_3d_status[0x00] & 0xf0000000)) {
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DRM_WRITE8(map, 0xb057, 8);
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while (0 != (DRM_READ32(map, 0x2800) & 0xf0000000)) {
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while (0 != ((--time_out) & 0xfff))
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/* empty */ ;
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@ -116,57 +112,53 @@ static void xgi_ge_hang_reset(volatile u8 *mmio_vbase)
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u8 old_36;
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DRM_INFO("Can not reset back 0x%x!\n",
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ge_3d_status[0x00]);
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DRM_READ32(map, 0x2800));
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*(mmio_vbase + 0xb057) = 0;
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DRM_WRITE8(map, 0xb057, 0);
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/* Have to use 3x5.36 to reset. */
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/* Save and close dynamic gating */
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old_3ce = *(mmio_vbase + 0x3ce);
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*(mmio_vbase + 0x3ce) = 0x2a;
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old_3cf = *(mmio_vbase + 0x3cf);
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*(mmio_vbase + 0x3cf) = old_3cf & 0xfe;
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old_3ce = DRM_READ8(map, 0x3ce);
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DRM_WRITE8(map, 0x3ce, 0x2a);
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old_3cf = DRM_READ8(map, 0x3cf);
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DRM_WRITE8(map, 0x3cf, old_3cf & 0xfe);
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/* Reset GE */
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old_index = *(mmio_vbase + 0x3d4);
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*(mmio_vbase + 0x3d4) = 0x36;
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old_36 = *(mmio_vbase + 0x3d5);
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*(mmio_vbase + 0x3d5) = old_36 | 0x10;
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old_index = DRM_READ8(map, 0x3d4);
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DRM_WRITE8(map, 0x3d4, 0x36);
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old_36 = DRM_READ8(map, 0x3d5);
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DRM_WRITE8(map, 0x3d5, old_36 | 0x10);
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while (0 != ((--time_out) & 0xfff))
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/* empty */ ;
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*(mmio_vbase + 0x3d5) = old_36;
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*(mmio_vbase + 0x3d4) = old_index;
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DRM_WRITE8(map, 0x3d5, old_36);
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DRM_WRITE8(map, 0x3d4, old_index);
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/* Restore dynamic gating */
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*(mmio_vbase + 0x3cf) = old_3cf;
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*(mmio_vbase + 0x3ce) = old_3ce;
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DRM_WRITE8(map, 0x3cf, old_3cf);
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DRM_WRITE8(map, 0x3ce, old_3ce);
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break;
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}
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}
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*(mmio_vbase + 0xb057) = 0;
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DRM_WRITE8(map, 0xb057, 0);
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}
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bool xgi_ge_irq_handler(struct xgi_info * info)
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{
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volatile u8 *const mmio_vbase = info->mmio_map->handle;
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volatile u32 *const ge_3d_status =
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(volatile u32 *)(mmio_vbase + 0x2800);
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const u32 int_status = ge_3d_status[4];
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const u32 int_status = DRM_READ32(info->mmio_map, 0x2810);
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bool is_support_auto_reset = FALSE;
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/* Check GE on/off */
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if (0 == (0xffffc0f0 & int_status)) {
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u32 old_pcie_cmd_fetch_Addr = ge_3d_status[0x0a];
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if (0 != (0x1000 & int_status)) {
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/* We got GE stall interrupt.
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*/
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ge_3d_status[0x04] = int_status | 0x04000000;
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DRM_WRITE32(info->mmio_map, 0x2810,
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int_status | 0x04000000);
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if (is_support_auto_reset) {
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static cycles_t last_tick;
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@ -174,7 +166,7 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
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/* OE II is busy. */
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if (!xgi_validate_signal(mmio_vbase)) {
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if (!xgi_validate_signal(info->mmio_map)) {
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/* Nothing but skip. */
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} else if (0 == continue_int_count++) {
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last_tick = get_cycles();
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@ -189,13 +181,14 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
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/* GE Hung up, need reset. */
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DRM_INFO("Reset GE!\n");
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xgi_ge_hang_reset(mmio_vbase);
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xgi_ge_hang_reset(info->mmio_map);
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}
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}
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}
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} else if (0 != (0x1 & int_status)) {
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s_invalid_begin++;
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ge_3d_status[0x04] = (int_status & ~0x01) | 0x04000000;
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DRM_WRITE32(info->mmio_map, 0x2810,
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(int_status & ~0x01) | 0x04000000);
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}
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return TRUE;
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@ -456,14 +449,38 @@ int xgi_restore_registers_ioctl(struct drm_device * dev, void * data,
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return 0;
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}
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#define WHOLD_GE_STATUS 0x2800
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/* Test everything except the "whole GE busy" bit, the "master engine busy"
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* bit, and the reserved bits [26:21].
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*/
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#define IDLE_MASK ~((1U<<31) | (1U<<28) | (0x3f<<21))
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void xgi_waitfor_pci_idle(struct xgi_info * info)
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{
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#define WHOLD_GE_STATUS 0x2800
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#define IDLE_MASK ~0x90200000
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unsigned int idleCount = 0;
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u32 old_status = 0;
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unsigned int same_count = 0;
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int idleCount = 0;
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while (idleCount < 5) {
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if (DRM_READ32(info->mmio_map, WHOLD_GE_STATUS) & IDLE_MASK) {
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const u32 status = DRM_READ32(info->mmio_map, WHOLD_GE_STATUS)
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& IDLE_MASK;
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if (status == old_status) {
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same_count++;
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if ((same_count % 100) == 0) {
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DRM_ERROR("GE status stuck at 0x%08x for %u iterations!\n",
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old_status, same_count);
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}
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} else {
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old_status = status;
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same_count = 0;
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}
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if (status != 0) {
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msleep(1);
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idleCount = 0;
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} else {
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idleCount++;
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