amdgpu: delete test configuration file
Json package dependence is removed from amdgpu_test, so this json configuration file is not needed any more. Suggested-by: Christian König <christian.koenig@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>main
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{
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"version": "0.0.1",
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"block": {
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"umc": {
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"index": 0
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},
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"gfx": {
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"index": 2,
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"subblock": {
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"gfx_cpc_scratch": 0,
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"gfx_cpc_ucode": 1,
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"gfx_dc_state_me1": 2,
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"gfx_dc_csinvoc_me1": 3,
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"gfx_dc_restore_me1": 4,
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"gfx_dc_state_me2": 5,
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"gfx_dc_csinvoc_me2": 6,
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"gfx_dc_restore_me2": 7,
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"gfx_cpf_roq_me2": 8,
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"gfx_cpf_roq_me1": 9,
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"gfx_cpf_tag": 10,
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"gfx_cpg_dma_roq": 11,
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"gfx_cpg_dma_tag": 12,
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"gfx_cpg_tag": 13,
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"gfx_gds_mem": 14,
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"gfx_gds_input_queue": 15,
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"gfx_gds_oa_phy_cmd_ram_mem": 16,
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"gfx_gds_oa_phy_data_ram_mem": 17,
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"gfx_gds_oa_pipe_mem": 18,
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"gfx_spi_sr_mem": 19,
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"gfx_sq_sgpr": 20,
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"gfx_sq_lds_d": 21,
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"gfx_sq_lds_i": 22,
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"gfx_sq_vgpr": 23,
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"gfx_sqc_inst_utcl1_lfifo": 24,
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"gfx_sqc_data_cu0_write_data_buf": 25,
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"gfx_sqc_data_cu0_utcl1_lfifo": 26,
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"gfx_sqc_data_cu1_write_data_buf": 27,
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"gfx_sqc_data_cu1_utcl1_lfifo": 28,
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"gfx_sqc_data_cu2_write_data_buf": 29,
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"gfx_sqc_data_cu2_utcl1_lfifo": 30,
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"gfx_sqc_inst_banka_tag_ram": 31,
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"gfx_sqc_inst_banka_utcl1_miss_fifo": 32,
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"gfx_sqc_inst_banka_miss_fifo": 33,
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"gfx_sqc_inst_banka_bank_ram": 34,
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"gfx_sqc_data_banka_tag_ram": 35,
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"gfx_sqc_data_banka_hit_fifo": 36,
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"gfx_sqc_data_banka_miss_fifo": 37,
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"gfx_sqc_data_banka_dirty_bit_ram": 38,
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"gfx_sqc_data_banka_bank_ram": 39,
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"gfx_sqc_inst_bankb_tag_ram": 40,
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"gfx_sqc_inst_bankb_utcl1_miss_fifo": 41,
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"gfx_sqc_inst_bankb_miss_fifo": 42,
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"gfx_sqc_inst_bankb_bank_ram": 43,
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"gfx_sqc_data_bankb_tag_ram": 44,
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"gfx_sqc_data_bankb_hit_fifo": 45,
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"gfx_sqc_data_bankb_miss_fifo": 46,
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"gfx_sqc_data_bankb_dirty_bit_ram": 47,
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"gfx_sqc_data_bankb_bank_ram": 48,
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"gfx_ta_fs_dfifo": 49,
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"gfx_ta_fs_afifo": 50,
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"gfx_ta_fl_lfifo": 51,
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"gfx_ta_fx_lfifo": 52,
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"gfx_ta_fs_cfifo": 53,
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"gfx_tca_hole_fifo": 54,
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"gfx_tca_req_fifo": 55,
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"gfx_tcc_cache_data": 56,
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"gfx_tcc_cache_data_bank_0_1": 57,
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"gfx_tcc_cache_data_bank_1_0": 58,
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"gfx_tcc_cache_data_bank_1_1": 59,
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"gfx_tcc_cache_dirty_bank_0": 60,
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"gfx_tcc_cache_dirty_bank_1": 61,
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"gfx_tcc_high_rate_tag": 62,
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"gfx_tcc_low_rate_tag": 63,
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"gfx_tcc_in_use_dec": 64,
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"gfx_tcc_in_use_transfer": 65,
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"gfx_tcc_return_data": 66,
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"gfx_tcc_return_control": 67,
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"gfx_tcc_uc_atomic_fifo": 68,
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"gfx_tcc_write_return": 69,
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"gfx_tcc_write_cache_read": 70,
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"gfx_tcc_src_fifo": 71,
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"gfx_tcc_src_fifo_next_ram": 72,
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"gfx_tcc_cache_tag_probe_fifo": 73,
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"gfx_tcc_latency_fifo": 74,
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"gfx_tcc_latency_fifo_next_ram": 75,
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"gfx_tcc_wrret_tag_write_return": 76,
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"gfx_tcc_atomic_return_buffer": 77,
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"gfx_tci_write_ram": 78,
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"gfx_tcp_cache_ram": 79,
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"gfx_tcp_lfifo_ram": 80,
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"gfx_tcp_cmd_fifo": 81,
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"gfx_tcp_vm_fifo": 82,
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"gfx_tcp_db_ram": 83,
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"gfx_tcp_utcl1_lfifo0": 84,
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"gfx_tcp_utcl1_lfifo1": 85,
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"gfx_td_ss_fifo_lo": 86,
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"gfx_td_ss_fifo_hi": 87,
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"gfx_td_cs_fifo": 88,
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"gfx_ea_dramrd_cmdmem": 89,
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"gfx_ea_dramwr_cmdmem": 90,
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"gfx_ea_dramwr_datamem": 91,
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"gfx_ea_rret_tagmem": 92,
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"gfx_ea_wret_tagmem": 93,
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"gfx_ea_gmird_cmdmem": 94,
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"gfx_ea_gmiwr_cmdmem": 95,
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"gfx_ea_gmiwr_datamem": 96,
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"gfx_ea_dramrd_pagemem": 97,
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"gfx_ea_dramwr_pagemem": 98,
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"gfx_ea_iord_cmdmem": 99,
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"gfx_ea_iowr_cmdmem": 100,
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"gfx_ea_iowr_datamem": 101,
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"gfx_ea_gmird_pagemem": 102,
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"gfx_ea_gmiwr_pagemem": 103,
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"gfx_ea_mam_d0mem": 104,
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"gfx_ea_mam_d1mem": 105,
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"gfx_ea_mam_d2mem": 106,
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"gfx_ea_mam_d3mem": 107,
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"utc_vml2_bank_cache": 108,
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"utc_vml2_walker": 109,
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"utc_atcl2_cache_2m_bank": 110,
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"utc_atcl2_cache_4k_bank": 111
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}
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},
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},
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"type": {
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"parity": 1,
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"single_correctable": 2,
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"multi_uncorrectable": 4,
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"poison": 8
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},
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"tests": [
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{
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"name": "ras_umc.1.0",
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"block": "umc",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_umc.1.0",
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"block": "umc",
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"type": "multi_uncorrectable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.1",
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"block": "gfx",
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"subblock": "gfx_cpc_ucode",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.10",
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"block": "gfx",
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"subblock": "gfx_cpf_tag",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.13",
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"block": "gfx",
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"subblock": "gfx_cpg_tag",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.21",
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"block": "gfx",
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"subblock": "gfx_sq_lds_d",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.28",
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"block": "gfx",
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"subblock": "gfx_sqc_data_cu1_utcl1_lfifo",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.31",
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"block": "gfx",
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"subblock": "gfx_sqc_inst_banka_tag_ram",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.40",
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"block": "gfx",
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"subblock": "gfx_sqc_inst_bankb_tag_ram",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.49",
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"block": "gfx",
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"subblock": "gfx_ta_fs_dfifo",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.56",
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"block": "gfx",
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"subblock": "gfx_tcc_cache_data",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.57",
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"block": "gfx",
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"subblock": "gfx_tcc_cache_data_bank_0_1",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.58",
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"block": "gfx",
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"subblock": "gfx_tcc_cache_data_bank_1_0",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.59",
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"block": "gfx",
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"subblock": "gfx_tcc_cache_data_bank_1_1",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.79",
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"block": "gfx",
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"subblock": "gfx_tcp_cache_ram",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.86",
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"block": "gfx",
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"subblock": "gfx_td_ss_fifo_lo",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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{
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"name": "ras_gfx.2.89",
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"block": "gfx",
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"subblock": "gfx_ea_dramrd_cmdmem",
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"type": "single_correctable",
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"address": 0,
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"value": 0
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},
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]
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}
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