radeon/ttm: add support for zeroing the contents of VRAM buffers
This uses a solid fill fastpath, falling back to the slow memset path.main
Dave Airlie
parent
203243eea5
commit
01b2e7368a
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@ -37,7 +37,7 @@ struct drm_ttm_backend *radeon_create_ttm_backend_entry(struct drm_device * dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if(dev_priv->flags & RADEON_IS_AGP)
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if (dev_priv->flags & RADEON_IS_AGP)
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return drm_agp_init_ttm(dev);
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else
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return ati_pcigart_init_ttm(dev, &dev_priv->gart_info, radeon_gart_flush);
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@ -58,9 +58,10 @@ int radeon_invalidate_caches(struct drm_device * dev, uint64_t flags)
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if (!dev_priv->cp_running)
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return 0;
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BEGIN_RING(4);
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RADEON_FLUSH_CACHE();
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RADEON_FLUSH_ZCACHE();
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BEGIN_RING(6);
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RADEON_PURGE_CACHE();
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RADEON_PURGE_ZCACHE();
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RADEON_WAIT_UNTIL_3D_IDLE();
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ADVANCE_RING();
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COMMIT_RING();
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return 0;
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@ -112,15 +113,17 @@ int radeon_init_mem_type(struct drm_device * dev, uint32_t type,
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return 0;
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}
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static void radeon_emit_copy_blit(struct drm_device * dev,
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uint32_t src_offset,
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uint32_t dst_offset,
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uint32_t pages, int direction)
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void radeon_emit_copy_blit(struct drm_device * dev,
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uint32_t src_offset,
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uint32_t dst_offset,
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uint32_t pages)
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{
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uint32_t cur_pages;
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uint32_t stride = PAGE_SIZE;
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uint32_t stride_bytes = PAGE_SIZE;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t format, height;
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uint32_t format, pitch;
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const uint32_t clip = (0x1fff) | (0x1fff << 16);
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uint32_t stride_pixels;
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RING_LOCALS;
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if (!dev_priv)
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@ -130,67 +133,171 @@ static void radeon_emit_copy_blit(struct drm_device * dev,
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format = RADEON_COLOR_FORMAT_ARGB8888;
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/* radeon limited to 16k stride */
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stride &= 0x3fff;
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stride_bytes &= 0x3fff;
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/* radeon pitch is /64 */
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pitch = stride_bytes / 64;
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stride_pixels = stride_bytes / 4;
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while(pages > 0) {
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cur_pages = pages;
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if (cur_pages > 2048)
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cur_pages = 2048;
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if (cur_pages > 8191)
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cur_pages = 8191;
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pages -= cur_pages;
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/* needs verification */
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BEGIN_RING(7);
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OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
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/* pages are in Y direction - height
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page width in X direction - width */
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BEGIN_RING(10);
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OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 8));
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OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
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RADEON_GMC_DST_PITCH_OFFSET_CNTL |
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RADEON_GMC_SRC_CLIPPING | RADEON_GMC_DST_CLIPPING |
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RADEON_GMC_BRUSH_NONE |
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(format << 8) |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_ROP3_S |
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RADEON_DP_SRC_SOURCE_MEMORY |
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RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
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if (direction) {
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OUT_RING((stride << 22) | (src_offset >> 10));
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OUT_RING((stride << 22) | (dst_offset >> 10));
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} else {
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OUT_RING((stride << 22) | (dst_offset >> 10));
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OUT_RING((stride << 22) | (src_offset >> 10));
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}
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OUT_RING(0);
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OUT_RING((pitch << 22) | (src_offset >> 10));
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OUT_RING((pitch << 22) | (dst_offset >> 10));
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OUT_RING(clip); // SRC _SC BOT_RITE
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OUT_RING(0); // SC_TOP_LEFT
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OUT_RING(clip); // SC_BOT_RITE
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OUT_RING(pages);
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OUT_RING(pages); /* x - y */
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OUT_RING((stride << 16) | cur_pages);
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OUT_RING(cur_pages | (stride_pixels << 16));
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ADVANCE_RING();
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}
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BEGIN_RING(2);
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BEGIN_RING(4);
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OUT_RING(CP_PACKET0(RADEON_RB2D_DSTCACHE_CTLSTAT, 0));
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OUT_RING(RADEON_RB2D_DC_FLUSH_ALL);
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RADEON_WAIT_UNTIL_2D_IDLE();
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ADVANCE_RING();
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COMMIT_RING();
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return;
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}
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static int radeon_move_blit(struct drm_buffer_object * bo,
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int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
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int radeon_move_blit(struct drm_buffer_object * bo,
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int evict, int no_wait, struct drm_bo_mem_reg *new_mem,
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struct drm_bo_mem_reg *old_mem)
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{
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struct drm_bo_mem_reg *old_mem = &bo->mem;
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int dir = 0;
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struct drm_device *dev = bo->dev;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t old_start, new_start;
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if ((old_mem->mem_type == new_mem->mem_type) &&
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(new_mem->mm_node->start <
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old_mem->mm_node->start + old_mem->mm_node->size)) {
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dir = 1;
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}
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old_start = old_mem->mm_node->start << PAGE_SHIFT;
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new_start = new_mem->mm_node->start << PAGE_SHIFT;
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if (old_mem->mem_type == DRM_BO_MEM_VRAM)
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old_start += dev_priv->fb_location;
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if (old_mem->mem_type == DRM_BO_MEM_TT)
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old_start += dev_priv->gart_vm_start;
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if (new_mem->mem_type == DRM_BO_MEM_VRAM)
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new_start += dev_priv->fb_location;
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if (new_mem->mem_type == DRM_BO_MEM_TT)
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new_start += dev_priv->gart_vm_start;
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radeon_emit_copy_blit(bo->dev,
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old_mem->mm_node->start << PAGE_SHIFT,
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new_mem->mm_node->start << PAGE_SHIFT,
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new_mem->num_pages, dir);
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old_start,
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new_start,
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new_mem->num_pages);
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/* invalidate the chip caches */
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return drm_bo_move_accel_cleanup(bo, evict, no_wait, 0,
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DRM_FENCE_TYPE_EXE, 0,
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new_mem);
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}
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void radeon_emit_solid_fill(struct drm_device * dev,
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uint32_t dst_offset,
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uint32_t pages, uint8_t value)
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{
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uint32_t cur_pages;
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uint32_t stride_bytes = PAGE_SIZE;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t format, pitch;
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const uint32_t clip = (0x1fff) | (0x1fff << 16);
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uint32_t stride_pixels;
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RING_LOCALS;
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if (!dev_priv)
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return;
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/* 32-bit copy format */
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format = RADEON_COLOR_FORMAT_ARGB8888;
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/* radeon limited to 16k stride */
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stride_bytes &= 0x3fff;
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/* radeon pitch is /64 */
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pitch = stride_bytes / 64;
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stride_pixels = stride_bytes / 4;
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while(pages > 0) {
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cur_pages = pages;
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if (cur_pages > 8191)
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cur_pages = 8191;
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pages -= cur_pages;
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/* pages are in Y direction - height
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page width in X direction - width */
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BEGIN_RING(8);
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OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 6));
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OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
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RADEON_GMC_DST_CLIPPING |
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RADEON_GMC_BRUSH_SOLID_COLOR |
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(format << 8) |
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RADEON_ROP3_S |
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RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
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OUT_RING((pitch << 22) | (dst_offset >> 10)); // PITCH
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OUT_RING(0); // SC_TOP_LEFT // DST CLIPPING
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OUT_RING(clip); // SC_BOT_RITE
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OUT_RING(0); // COLOR
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OUT_RING(pages); /* x - y */
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OUT_RING(cur_pages | (stride_pixels << 16));
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ADVANCE_RING();
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}
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BEGIN_RING(4);
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OUT_RING(CP_PACKET0(RADEON_RB2D_DSTCACHE_CTLSTAT, 0));
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OUT_RING(RADEON_RB2D_DC_FLUSH_ALL);
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RADEON_WAIT_UNTIL_2D_IDLE();
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ADVANCE_RING();
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COMMIT_RING();
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return;
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}
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int radeon_move_zero_fill(struct drm_buffer_object * bo,
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int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
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{
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struct drm_device *dev = bo->dev;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t new_start;
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new_start = new_mem->mm_node->start << PAGE_SHIFT;
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if (new_mem->mem_type == DRM_BO_MEM_VRAM)
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new_start += dev_priv->fb_location;
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radeon_emit_solid_fill(bo->dev,
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new_start,
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new_mem->num_pages, 0);
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/* invalidate the chip caches */
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return drm_bo_move_accel_cleanup(bo, 1, no_wait, 0,
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DRM_FENCE_TYPE_EXE, 0,
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new_mem);
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}
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static int radeon_move_flip(struct drm_buffer_object * bo,
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int evict, int no_wait, struct drm_bo_mem_reg * new_mem)
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{
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@ -200,8 +307,7 @@ static int radeon_move_flip(struct drm_buffer_object * bo,
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tmp_mem = *new_mem;
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tmp_mem.mm_node = NULL;
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// tmp_mem.mask = DRM_BO_FLAG_MEM_TT |
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// DRM_BO_FLAG_CACHED | DRM_BO_FLAG_FORCE_CACHING;
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tmp_mem.proposed_flags = DRM_BO_FLAG_MEM_TT;
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ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
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if (ret)
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@ -211,7 +317,7 @@ static int radeon_move_flip(struct drm_buffer_object * bo,
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if (ret)
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goto out_cleanup;
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ret = radeon_move_blit(bo, 1, no_wait, &tmp_mem);
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ret = radeon_move_blit(bo, 1, no_wait, &tmp_mem, &bo->mem);
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if (ret)
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goto out_cleanup;
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@ -227,25 +333,90 @@ out_cleanup:
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return ret;
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}
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int radeon_move(struct drm_buffer_object * bo,
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int evict, int no_wait, struct drm_bo_mem_reg * new_mem)
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{
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static int radeon_move_vram(struct drm_buffer_object * bo,
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int evict, int no_wait, struct drm_bo_mem_reg * new_mem)
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{
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struct drm_device *dev = bo->dev;
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struct drm_bo_mem_reg tmp_mem;
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struct drm_bo_mem_reg *old_mem = &bo->mem;
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int ret;
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bool was_local = false;
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/* old - LOCAL memory node bo->mem
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tmp - TT type memory node
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new - VRAM memory node */
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tmp_mem = *old_mem;
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tmp_mem.mm_node = NULL;
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return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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#if 0
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DRM_DEBUG("\n");
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if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
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return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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} else if (new_mem->mem_type == DRM_BO_MEM_LOCAL) {
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tmp_mem.proposed_flags = DRM_BO_FLAG_MEM_TT;
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ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
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if (ret)
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return ret;
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}
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if (!bo->ttm) {
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ret = drm_bo_add_ttm(bo);
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if (ret)
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goto out_cleanup;
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}
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if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
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ret = drm_bo_move_ttm(bo, evict, no_wait, &tmp_mem);
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if (ret)
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return ret;
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}
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ret = radeon_move_blit(bo, 1, no_wait, new_mem, &bo->mem);
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if (ret)
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goto out_cleanup;
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out_cleanup:
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if (tmp_mem.mm_node) {
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mutex_lock(&dev->struct_mutex);
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if (tmp_mem.mm_node != bo->pinned_node)
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drm_mm_put_block(tmp_mem.mm_node);
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tmp_mem.mm_node = NULL;
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mutex_unlock(&dev->struct_mutex);
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}
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return ret;
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}
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int radeon_move(struct drm_buffer_object * bo,
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int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
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{
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struct drm_device *dev = bo->dev;
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struct drm_bo_mem_reg *old_mem = &bo->mem;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if (!dev_priv->cp_running)
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goto fallback;
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if (bo->mem.flags & DRM_BO_FLAG_CLEAN) /* need to implement solid fill */
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{
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if (radeon_move_zero_fill(bo, evict, no_wait, new_mem))
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return drm_bo_move_zero(bo, evict, no_wait, new_mem);
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return 0;
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}
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if (new_mem->mem_type == DRM_BO_MEM_VRAM) {
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if (radeon_move_vram(bo, evict, no_wait, new_mem))
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goto fallback;
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} else if (new_mem->mem_type == DRM_BO_MEM_LOCAL){
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if (radeon_move_flip(bo, evict, no_wait, new_mem))
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return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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goto fallback;
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} else {
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if (radeon_move_blit(bo, evict, no_wait, new_mem))
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return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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if (radeon_move_flip(bo, evict, no_wait, new_mem))
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goto fallback;
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}
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return 0;
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#endif
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fallback:
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if (bo->mem.flags & DRM_BO_FLAG_CLEAN)
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return drm_bo_move_zero(bo, evict, no_wait, new_mem);
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else
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return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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}
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