intel: Prepare for BLT ring split.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>main
parent
c5286f4a87
commit
057fab3382
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@ -206,6 +206,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
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@ -276,6 +277,7 @@ typedef struct drm_i915_irq_wait {
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#define I915_PARAM_HAS_PAGEFLIPPING 8
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#define I915_PARAM_HAS_PAGEFLIPPING 8
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#define I915_PARAM_HAS_EXECBUF2 9
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#define I915_PARAM_HAS_EXECBUF2 9
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#define I915_PARAM_HAS_BSD 10
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#define I915_PARAM_HAS_BSD 10
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#define I915_PARAM_HAS_BLT 11
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typedef struct drm_i915_getparam {
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typedef struct drm_i915_getparam {
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int param;
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int param;
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@ -617,8 +619,11 @@ struct drm_i915_gem_execbuffer2 {
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__u32 num_cliprects;
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__u32 num_cliprects;
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/** This is a struct drm_clip_rect *cliprects */
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/** This is a struct drm_clip_rect *cliprects */
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__u64 cliprects_ptr;
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__u64 cliprects_ptr;
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#define I915_EXEC_RING_MASK (7<<0)
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#define I915_EXEC_DEFAULT (0<<0)
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#define I915_EXEC_RENDER (1<<0)
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#define I915_EXEC_RENDER (1<<0)
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#define I915_EXEC_BSD (1<<1)
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#define I915_EXEC_BSD (2<<0)
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#define I915_EXEC_BLT (3<<0)
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__u64 flags;
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__u64 flags;
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__u64 rsvd1;
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__u64 rsvd1;
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__u64 rsvd2;
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__u64 rsvd2;
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@ -99,6 +99,8 @@ typedef struct _drm_intel_bufmgr_gem {
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int available_fences;
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int available_fences;
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int pci_device;
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int pci_device;
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int gen;
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int gen;
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char has_bsd;
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char has_blt;
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char bo_reuse;
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char bo_reuse;
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char fenced_relocs;
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char fenced_relocs;
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} drm_intel_bufmgr_gem;
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} drm_intel_bufmgr_gem;
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@ -1545,8 +1547,21 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_execbuffer2 execbuf;
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int ret, i;
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int ret, i;
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if ((ring_flag != I915_EXEC_RENDER) && (ring_flag != I915_EXEC_BSD))
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switch (ring_flag) {
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default:
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return -EINVAL;
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return -EINVAL;
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case I915_EXEC_BLT:
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if (!bufmgr_gem->has_blt)
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return -EINVAL;
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break;
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case I915_EXEC_BSD:
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if (!bufmgr_gem->has_bsd)
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return -EINVAL;
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break;
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case I915_EXEC_RENDER:
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case I915_EXEC_DEFAULT:
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break;
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}
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pthread_mutex_lock(&bufmgr_gem->lock);
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pthread_mutex_lock(&bufmgr_gem->lock);
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/* Update indices and set up the validate list. */
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/* Update indices and set up the validate list. */
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@ -2054,7 +2069,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
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struct drm_i915_gem_get_aperture aperture;
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struct drm_i915_gem_get_aperture aperture;
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drm_i915_getparam_t gp;
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drm_i915_getparam_t gp;
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int ret;
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int ret;
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int exec2 = 0, has_bsd = 0;
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int exec2 = 0;
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bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
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bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
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if (bufmgr_gem == NULL)
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if (bufmgr_gem == NULL)
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@ -2107,8 +2122,11 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
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gp.param = I915_PARAM_HAS_BSD;
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gp.param = I915_PARAM_HAS_BSD;
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ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
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ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
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if (!ret)
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bufmgr_gem->has_bsd = ret == 0;
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has_bsd = 1;
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gp.param = I915_PARAM_HAS_BLT;
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ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
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bufmgr_gem->has_blt = ret == 0;
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if (bufmgr_gem->gen < 4) {
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if (bufmgr_gem->gen < 4) {
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gp.param = I915_PARAM_NUM_FENCES_AVAIL;
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gp.param = I915_PARAM_NUM_FENCES_AVAIL;
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@ -2165,7 +2183,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
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/* Use the new one if available */
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/* Use the new one if available */
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if (exec2) {
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if (exec2) {
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bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
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bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
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if (has_bsd)
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if (bufmgr_gem->has_bsd|bufmgr_gem->has_blt)
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bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
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bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
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} else
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} else
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bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
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bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
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