parent
963ad33cb6
commit
062751ac47
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@ -855,25 +855,23 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
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/* Initialize the memory controller */
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/* Initialize the memory controller */
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RADEON_WRITE( RADEON_MC_FB_LOCATION,
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RADEON_WRITE( RADEON_MC_FB_LOCATION,
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(dev_priv->agp_vm_start - 1) & 0xffff0000 );
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(dev_priv->gart_vm_start - 1) & 0xffff0000 );
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if ( !dev_priv->is_pci ) {
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RADEON_WRITE( RADEON_MC_AGP_LOCATION,
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(((dev_priv->agp_vm_start - 1 +
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dev_priv->agp_size) & 0xffff0000) |
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(dev_priv->agp_vm_start >> 16)) );
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}
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#if __REALLY_HAVE_AGP
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#if __REALLY_HAVE_AGP
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if ( !dev_priv->is_pci )
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if ( !dev_priv->is_pci ) {
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RADEON_WRITE( RADEON_MC_AGP_LOCATION,
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(((dev_priv->gart_vm_start - 1 +
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dev_priv->gart_size) & 0xffff0000) |
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(dev_priv->gart_vm_start >> 16)) );
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ring_start = (dev_priv->cp_ring->offset
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ring_start = (dev_priv->cp_ring->offset
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- dev->agp->base
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- dev->agp->base
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+ dev_priv->agp_vm_start);
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+ dev_priv->gart_vm_start);
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else
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} else
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#endif
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#endif
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ring_start = (dev_priv->cp_ring->offset
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ring_start = (dev_priv->cp_ring->offset
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- dev->sg->handle
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- dev->sg->handle
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+ dev_priv->agp_vm_start);
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+ dev_priv->gart_vm_start);
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RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
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RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
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@ -891,7 +889,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
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RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
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RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
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dev_priv->ring_rptr->offset
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dev_priv->ring_rptr->offset
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- dev->agp->base
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- dev->agp->base
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+ dev_priv->agp_vm_start);
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+ dev_priv->gart_vm_start);
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} else
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} else
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#endif
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#endif
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{
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{
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@ -989,11 +987,11 @@ static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
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/* set address range for PCI address translate
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/* set address range for PCI address translate
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*/
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*/
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RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
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RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
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RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
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RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
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+ dev_priv->agp_size - 1);
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+ dev_priv->gart_size - 1);
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/* Turn off AGP aperture -- is this required for PCIGART?
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/* Turn off AGP aperture -- is this required for PCI GART?
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*/
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*/
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RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
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RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
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RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
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RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
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@ -1117,7 +1115,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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dev_priv->ring_offset = init->ring_offset;
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dev_priv->ring_offset = init->ring_offset;
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dev_priv->ring_rptr_offset = init->ring_rptr_offset;
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dev_priv->ring_rptr_offset = init->ring_rptr_offset;
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dev_priv->buffers_offset = init->buffers_offset;
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dev_priv->buffers_offset = init->buffers_offset;
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dev_priv->agp_textures_offset = init->agp_textures_offset;
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dev_priv->gart_textures_offset = init->gart_textures_offset;
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if(!dev_priv->sarea) {
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if(!dev_priv->sarea) {
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DRM_ERROR("could not find sarea!\n");
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DRM_ERROR("could not find sarea!\n");
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@ -1162,11 +1160,10 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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return DRM_ERR(EINVAL);
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return DRM_ERR(EINVAL);
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}
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}
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if ( !dev_priv->is_pci ) {
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if ( init->gart_textures_offset ) {
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DRM_FIND_MAP( dev_priv->agp_textures,
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DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset );
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init->agp_textures_offset );
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if ( !dev_priv->gart_textures ) {
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if(!dev_priv->agp_textures) {
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DRM_ERROR("could not find GART texture region!\n");
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DRM_ERROR("could not find agp texture region!\n");
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dev->dev_private = (void *)dev_priv;
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dev->dev_private = (void *)dev_priv;
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radeon_do_cleanup_cp(dev);
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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return DRM_ERR(EINVAL);
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@ -1208,25 +1205,25 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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}
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}
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dev_priv->agp_size = init->agp_size;
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dev_priv->gart_size = init->gart_size;
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dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
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dev_priv->gart_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
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#if __REALLY_HAVE_AGP
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#if __REALLY_HAVE_AGP
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if ( !dev_priv->is_pci )
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if ( !dev_priv->is_pci )
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dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
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dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
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- dev->agp->base
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- dev->agp->base
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+ dev_priv->agp_vm_start);
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+ dev_priv->gart_vm_start);
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else
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else
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#endif
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#endif
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dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
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dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
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- dev->sg->handle
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- dev->sg->handle
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+ dev_priv->agp_vm_start);
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+ dev_priv->gart_vm_start);
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DRM_DEBUG( "dev_priv->agp_size %d\n",
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DRM_DEBUG( "dev_priv->gart_size %d\n",
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dev_priv->agp_size );
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dev_priv->gart_size );
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DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
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DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
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dev_priv->agp_vm_start );
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dev_priv->gart_vm_start );
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DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
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DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
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dev_priv->agp_buffers_offset );
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dev_priv->gart_buffers_offset );
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dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
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dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
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dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
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dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
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@ -1463,7 +1460,7 @@ void radeon_do_release( drm_device_t *dev )
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RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
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RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
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/* Free memory heap structures */
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/* Free memory heap structures */
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radeon_mem_takedown( &(dev_priv->agp_heap) );
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radeon_mem_takedown( &(dev_priv->gart_heap) );
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radeon_mem_takedown( &(dev_priv->fb_heap) );
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radeon_mem_takedown( &(dev_priv->fb_heap) );
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/* deallocate kernel resources */
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/* deallocate kernel resources */
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@ -214,11 +214,11 @@ typedef union {
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#define RADEON_NR_SAREA_CLIPRECTS 12
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#define RADEON_NR_SAREA_CLIPRECTS 12
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/* There are 2 heaps (local/AGP). Each region within a heap is a
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/* There are 2 heaps (local/GART). Each region within a heap is a
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* minimum of 64k, and there are at most 64 of them per heap.
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* minimum of 64k, and there are at most 64 of them per heap.
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*/
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*/
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#define RADEON_LOCAL_TEX_HEAP 0
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#define RADEON_LOCAL_TEX_HEAP 0
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#define RADEON_AGP_TEX_HEAP 1
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#define RADEON_GART_TEX_HEAP 1
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#define RADEON_NR_TEX_HEAPS 2
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#define RADEON_NR_TEX_HEAPS 2
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#define RADEON_NR_TEX_REGIONS 64
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#define RADEON_NR_TEX_REGIONS 64
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#define RADEON_LOG_TEX_GRANULARITY 16
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#define RADEON_LOG_TEX_GRANULARITY 16
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@ -400,7 +400,7 @@ typedef struct drm_radeon_init {
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unsigned long sarea_priv_offset;
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unsigned long sarea_priv_offset;
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int is_pci;
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int is_pci;
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int cp_mode;
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int cp_mode;
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int agp_size;
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int gart_size;
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int ring_size;
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int ring_size;
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int usec_timeout;
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int usec_timeout;
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@ -415,7 +415,7 @@ typedef struct drm_radeon_init {
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unsigned long ring_offset;
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unsigned long ring_offset;
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unsigned long ring_rptr_offset;
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unsigned long ring_rptr_offset;
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unsigned long buffers_offset;
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unsigned long buffers_offset;
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unsigned long agp_textures_offset;
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unsigned long gart_textures_offset;
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} drm_radeon_init_t;
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} drm_radeon_init_t;
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typedef struct drm_radeon_cp_stop {
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typedef struct drm_radeon_cp_stop {
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@ -525,18 +525,18 @@ typedef struct drm_radeon_indirect {
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/* 1.3: An ioctl to get parameters that aren't available to the 3d
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/* 1.3: An ioctl to get parameters that aren't available to the 3d
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* client any other way.
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* client any other way.
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*/
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*/
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#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */
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#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
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#define RADEON_PARAM_LAST_FRAME 2
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#define RADEON_PARAM_LAST_FRAME 2
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#define RADEON_PARAM_LAST_DISPATCH 3
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#define RADEON_PARAM_LAST_DISPATCH 3
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#define RADEON_PARAM_LAST_CLEAR 4
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#define RADEON_PARAM_LAST_CLEAR 4
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/* Added with DRM version 1.6. */
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/* Added with DRM version 1.6. */
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#define RADEON_PARAM_IRQ_NR 5
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#define RADEON_PARAM_IRQ_NR 5
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#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */
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#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
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/* Added with DRM version 1.8. */
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/* Added with DRM version 1.8. */
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#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
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#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
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#define RADEON_PARAM_STATUS_HANDLE 8
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#define RADEON_PARAM_STATUS_HANDLE 8
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#define RADEON_PARAM_SAREA_HANDLE 9
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#define RADEON_PARAM_SAREA_HANDLE 9
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#define RADEON_PARAM_AGP_TEX_HANDLE 10
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#define RADEON_PARAM_GART_TEX_HANDLE 10
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typedef struct drm_radeon_getparam {
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typedef struct drm_radeon_getparam {
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int param;
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int param;
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@ -545,14 +545,14 @@ typedef struct drm_radeon_getparam {
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/* 1.6: Set up a memory manager for regions of shared memory:
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/* 1.6: Set up a memory manager for regions of shared memory:
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*/
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*/
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#define RADEON_MEM_REGION_AGP 1
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#define RADEON_MEM_REGION_GART 1
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#define RADEON_MEM_REGION_FB 2
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#define RADEON_MEM_REGION_FB 2
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typedef struct drm_radeon_mem_alloc {
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typedef struct drm_radeon_mem_alloc {
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int region;
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int region;
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int alignment;
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int alignment;
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int size;
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int size;
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int *region_offset; /* offset from start of fb or agp */
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int *region_offset; /* offset from start of fb or GART */
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} drm_radeon_mem_alloc_t;
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} drm_radeon_mem_alloc_t;
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typedef struct drm_radeon_mem_free {
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typedef struct drm_radeon_mem_free {
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@ -73,9 +73,9 @@ typedef struct drm_radeon_private {
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drm_radeon_ring_buffer_t ring;
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drm_radeon_ring_buffer_t ring;
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drm_radeon_sarea_t *sarea_priv;
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drm_radeon_sarea_t *sarea_priv;
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int agp_size;
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int gart_size;
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u32 agp_vm_start;
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u32 gart_vm_start;
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unsigned long agp_buffers_offset;
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unsigned long gart_buffers_offset;
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int cp_mode;
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int cp_mode;
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int cp_running;
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int cp_running;
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@ -130,7 +130,7 @@ typedef struct drm_radeon_private {
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unsigned long ring_offset;
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unsigned long ring_offset;
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unsigned long ring_rptr_offset;
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unsigned long ring_rptr_offset;
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unsigned long buffers_offset;
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unsigned long buffers_offset;
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unsigned long agp_textures_offset;
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unsigned long gart_textures_offset;
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drm_local_map_t *sarea;
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drm_local_map_t *sarea;
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drm_local_map_t *fb;
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drm_local_map_t *fb;
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drm_local_map_t *cp_ring;
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drm_local_map_t *cp_ring;
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drm_local_map_t *ring_rptr;
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drm_local_map_t *ring_rptr;
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drm_local_map_t *buffers;
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drm_local_map_t *buffers;
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drm_local_map_t *agp_textures;
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drm_local_map_t *gart_textures;
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struct mem_block *agp_heap;
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struct mem_block *gart_heap;
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struct mem_block *fb_heap;
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struct mem_block *fb_heap;
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/* SW interrupt */
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/* SW interrupt */
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@ -1,4 +1,4 @@
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/* radeon_mem.c -- Simple agp/fb memory manager for radeon -*- linux-c -*-
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/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*-
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*
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*
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* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
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* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
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*
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*
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@ -35,7 +35,7 @@
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#include "radeon_drm.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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#include "radeon_drv.h"
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/* Very simple allocator for agp memory, working on a static range
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/* Very simple allocator for GART memory, working on a static range
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* already mapped into each client's address space.
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* already mapped into each client's address space.
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*/
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*/
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@ -212,8 +212,8 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv,
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int region )
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int region )
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{
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{
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switch( region ) {
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switch( region ) {
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case RADEON_MEM_REGION_AGP:
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case RADEON_MEM_REGION_GART:
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return &dev_priv->agp_heap;
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return &dev_priv->gart_heap;
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case RADEON_MEM_REGION_FB:
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case RADEON_MEM_REGION_FB:
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return &dev_priv->fb_heap;
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return &dev_priv->fb_heap;
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default:
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default:
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@ -893,7 +893,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
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int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
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int numverts = (int)prim->numverts;
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int numverts = (int)prim->numverts;
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int nbox = sarea_priv->nbox;
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int nbox = sarea_priv->nbox;
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int i = 0;
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int i = 0;
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@ -966,7 +966,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
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buf->idx, start, end );
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buf->idx, start, end );
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if ( start != end ) {
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if ( start != end ) {
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int offset = (dev_priv->agp_buffers_offset
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int offset = (dev_priv->gart_buffers_offset
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+ buf->offset + start);
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+ buf->offset + start);
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int dwords = (end - start + 3) / sizeof(u32);
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int dwords = (end - start + 3) / sizeof(u32);
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@ -999,7 +999,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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int offset = dev_priv->agp_buffers_offset + prim->offset;
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int offset = dev_priv->gart_buffers_offset + prim->offset;
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u32 *data;
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u32 *data;
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int dwords;
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int dwords;
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int i = 0;
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int i = 0;
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@ -2159,8 +2159,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
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DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
|
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
|
||||||
|
|
||||||
switch( param.param ) {
|
switch( param.param ) {
|
||||||
case RADEON_PARAM_AGP_BUFFER_OFFSET:
|
case RADEON_PARAM_GART_BUFFER_OFFSET:
|
||||||
value = dev_priv->agp_buffers_offset;
|
value = dev_priv->gart_buffers_offset;
|
||||||
break;
|
break;
|
||||||
case RADEON_PARAM_LAST_FRAME:
|
case RADEON_PARAM_LAST_FRAME:
|
||||||
dev_priv->stats.last_frame_reads++;
|
dev_priv->stats.last_frame_reads++;
|
||||||
|
@ -2176,8 +2176,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
|
||||||
case RADEON_PARAM_IRQ_NR:
|
case RADEON_PARAM_IRQ_NR:
|
||||||
value = dev->irq;
|
value = dev->irq;
|
||||||
break;
|
break;
|
||||||
case RADEON_PARAM_AGP_BASE:
|
case RADEON_PARAM_GART_BASE:
|
||||||
value = dev_priv->agp_vm_start;
|
value = dev_priv->gart_vm_start;
|
||||||
break;
|
break;
|
||||||
case RADEON_PARAM_REGISTER_HANDLE:
|
case RADEON_PARAM_REGISTER_HANDLE:
|
||||||
value = dev_priv->mmio_offset;
|
value = dev_priv->mmio_offset;
|
||||||
|
@ -2189,8 +2189,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
|
||||||
/* The lock is the first dword in the sarea. */
|
/* The lock is the first dword in the sarea. */
|
||||||
value = (int)dev->lock.hw_lock;
|
value = (int)dev->lock.hw_lock;
|
||||||
break;
|
break;
|
||||||
case RADEON_PARAM_AGP_TEX_HANDLE:
|
case RADEON_PARAM_GART_TEX_HANDLE:
|
||||||
value = dev_priv->agp_textures_offset;
|
value = dev_priv->gart_textures_offset;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return DRM_ERR(EINVAL);
|
return DRM_ERR(EINVAL);
|
||||||
|
|
|
@ -68,11 +68,11 @@
|
||||||
* 1.5 - Add r200 packets to cmdbuf ioctl
|
* 1.5 - Add r200 packets to cmdbuf ioctl
|
||||||
* - Add r200 function to init ioctl
|
* - Add r200 function to init ioctl
|
||||||
* - Add 'scalar2' instruction to cmdbuf
|
* - Add 'scalar2' instruction to cmdbuf
|
||||||
* 1.6 - Add static agp memory manager
|
* 1.6 - Add static GART memory manager
|
||||||
* Add irq handler (won't be turned on unless X server knows to)
|
* Add irq handler (won't be turned on unless X server knows to)
|
||||||
* Add irq ioctls and irq_active getparam.
|
* Add irq ioctls and irq_active getparam.
|
||||||
* Add wait command for cmdbuf ioctl
|
* Add wait command for cmdbuf ioctl
|
||||||
* Add agp offset query for getparam
|
* Add GART offset query for getparam
|
||||||
* 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
|
* 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
|
||||||
* and R200_PP_CUBIC_OFFSET_F1_[0..5].
|
* and R200_PP_CUBIC_OFFSET_F1_[0..5].
|
||||||
* Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
|
* Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
|
||||||
|
@ -113,7 +113,7 @@
|
||||||
|
|
||||||
/* When a client dies:
|
/* When a client dies:
|
||||||
* - Check for and clean up flipped page state
|
* - Check for and clean up flipped page state
|
||||||
* - Free any alloced agp memory.
|
* - Free any alloced GART memory.
|
||||||
*
|
*
|
||||||
* DRM infrastructure takes care of reclaiming dma buffers.
|
* DRM infrastructure takes care of reclaiming dma buffers.
|
||||||
*/
|
*/
|
||||||
|
@ -124,7 +124,7 @@ do { \
|
||||||
if ( dev_priv->page_flipping ) { \
|
if ( dev_priv->page_flipping ) { \
|
||||||
radeon_do_cleanup_pageflip( dev ); \
|
radeon_do_cleanup_pageflip( dev ); \
|
||||||
} \
|
} \
|
||||||
radeon_mem_release( filp, dev_priv->agp_heap ); \
|
radeon_mem_release( filp, dev_priv->gart_heap ); \
|
||||||
radeon_mem_release( filp, dev_priv->fb_heap ); \
|
radeon_mem_release( filp, dev_priv->fb_heap ); \
|
||||||
} \
|
} \
|
||||||
} while (0)
|
} while (0)
|
||||||
|
|
|
@ -855,25 +855,23 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
|
||||||
|
|
||||||
/* Initialize the memory controller */
|
/* Initialize the memory controller */
|
||||||
RADEON_WRITE( RADEON_MC_FB_LOCATION,
|
RADEON_WRITE( RADEON_MC_FB_LOCATION,
|
||||||
(dev_priv->agp_vm_start - 1) & 0xffff0000 );
|
(dev_priv->gart_vm_start - 1) & 0xffff0000 );
|
||||||
|
|
||||||
if ( !dev_priv->is_pci ) {
|
|
||||||
RADEON_WRITE( RADEON_MC_AGP_LOCATION,
|
|
||||||
(((dev_priv->agp_vm_start - 1 +
|
|
||||||
dev_priv->agp_size) & 0xffff0000) |
|
|
||||||
(dev_priv->agp_vm_start >> 16)) );
|
|
||||||
}
|
|
||||||
|
|
||||||
#if __REALLY_HAVE_AGP
|
#if __REALLY_HAVE_AGP
|
||||||
if ( !dev_priv->is_pci )
|
if ( !dev_priv->is_pci ) {
|
||||||
|
RADEON_WRITE( RADEON_MC_AGP_LOCATION,
|
||||||
|
(((dev_priv->gart_vm_start - 1 +
|
||||||
|
dev_priv->gart_size) & 0xffff0000) |
|
||||||
|
(dev_priv->gart_vm_start >> 16)) );
|
||||||
|
|
||||||
ring_start = (dev_priv->cp_ring->offset
|
ring_start = (dev_priv->cp_ring->offset
|
||||||
- dev->agp->base
|
- dev->agp->base
|
||||||
+ dev_priv->agp_vm_start);
|
+ dev_priv->gart_vm_start);
|
||||||
else
|
} else
|
||||||
#endif
|
#endif
|
||||||
ring_start = (dev_priv->cp_ring->offset
|
ring_start = (dev_priv->cp_ring->offset
|
||||||
- dev->sg->handle
|
- dev->sg->handle
|
||||||
+ dev_priv->agp_vm_start);
|
+ dev_priv->gart_vm_start);
|
||||||
|
|
||||||
RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
|
RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
|
||||||
|
|
||||||
|
@ -891,7 +889,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
|
||||||
RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
|
RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
|
||||||
dev_priv->ring_rptr->offset
|
dev_priv->ring_rptr->offset
|
||||||
- dev->agp->base
|
- dev->agp->base
|
||||||
+ dev_priv->agp_vm_start);
|
+ dev_priv->gart_vm_start);
|
||||||
} else
|
} else
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
|
@ -989,11 +987,11 @@ static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
|
||||||
|
|
||||||
/* set address range for PCI address translate
|
/* set address range for PCI address translate
|
||||||
*/
|
*/
|
||||||
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
|
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
|
||||||
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
|
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
|
||||||
+ dev_priv->agp_size - 1);
|
+ dev_priv->gart_size - 1);
|
||||||
|
|
||||||
/* Turn off AGP aperture -- is this required for PCIGART?
|
/* Turn off AGP aperture -- is this required for PCI GART?
|
||||||
*/
|
*/
|
||||||
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
|
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
|
||||||
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
|
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
|
||||||
|
@ -1117,7 +1115,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
|
||||||
dev_priv->ring_offset = init->ring_offset;
|
dev_priv->ring_offset = init->ring_offset;
|
||||||
dev_priv->ring_rptr_offset = init->ring_rptr_offset;
|
dev_priv->ring_rptr_offset = init->ring_rptr_offset;
|
||||||
dev_priv->buffers_offset = init->buffers_offset;
|
dev_priv->buffers_offset = init->buffers_offset;
|
||||||
dev_priv->agp_textures_offset = init->agp_textures_offset;
|
dev_priv->gart_textures_offset = init->gart_textures_offset;
|
||||||
|
|
||||||
if(!dev_priv->sarea) {
|
if(!dev_priv->sarea) {
|
||||||
DRM_ERROR("could not find sarea!\n");
|
DRM_ERROR("could not find sarea!\n");
|
||||||
|
@ -1162,11 +1160,10 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
|
||||||
return DRM_ERR(EINVAL);
|
return DRM_ERR(EINVAL);
|
||||||
}
|
}
|
||||||
|
|
||||||
if ( !dev_priv->is_pci ) {
|
if ( init->gart_textures_offset ) {
|
||||||
DRM_FIND_MAP( dev_priv->agp_textures,
|
DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset );
|
||||||
init->agp_textures_offset );
|
if ( !dev_priv->gart_textures ) {
|
||||||
if(!dev_priv->agp_textures) {
|
DRM_ERROR("could not find GART texture region!\n");
|
||||||
DRM_ERROR("could not find agp texture region!\n");
|
|
||||||
dev->dev_private = (void *)dev_priv;
|
dev->dev_private = (void *)dev_priv;
|
||||||
radeon_do_cleanup_cp(dev);
|
radeon_do_cleanup_cp(dev);
|
||||||
return DRM_ERR(EINVAL);
|
return DRM_ERR(EINVAL);
|
||||||
|
@ -1208,25 +1205,25 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
dev_priv->agp_size = init->agp_size;
|
dev_priv->gart_size = init->gart_size;
|
||||||
dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
|
dev_priv->gart_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
|
||||||
#if __REALLY_HAVE_AGP
|
#if __REALLY_HAVE_AGP
|
||||||
if ( !dev_priv->is_pci )
|
if ( !dev_priv->is_pci )
|
||||||
dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
|
dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
|
||||||
- dev->agp->base
|
- dev->agp->base
|
||||||
+ dev_priv->agp_vm_start);
|
+ dev_priv->gart_vm_start);
|
||||||
else
|
else
|
||||||
#endif
|
#endif
|
||||||
dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
|
dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
|
||||||
- dev->sg->handle
|
- dev->sg->handle
|
||||||
+ dev_priv->agp_vm_start);
|
+ dev_priv->gart_vm_start);
|
||||||
|
|
||||||
DRM_DEBUG( "dev_priv->agp_size %d\n",
|
DRM_DEBUG( "dev_priv->gart_size %d\n",
|
||||||
dev_priv->agp_size );
|
dev_priv->gart_size );
|
||||||
DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
|
DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
|
||||||
dev_priv->agp_vm_start );
|
dev_priv->gart_vm_start );
|
||||||
DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
|
DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
|
||||||
dev_priv->agp_buffers_offset );
|
dev_priv->gart_buffers_offset );
|
||||||
|
|
||||||
dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
|
dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
|
||||||
dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
|
dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
|
||||||
|
@ -1463,7 +1460,7 @@ void radeon_do_release( drm_device_t *dev )
|
||||||
RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
|
RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
|
||||||
|
|
||||||
/* Free memory heap structures */
|
/* Free memory heap structures */
|
||||||
radeon_mem_takedown( &(dev_priv->agp_heap) );
|
radeon_mem_takedown( &(dev_priv->gart_heap) );
|
||||||
radeon_mem_takedown( &(dev_priv->fb_heap) );
|
radeon_mem_takedown( &(dev_priv->fb_heap) );
|
||||||
|
|
||||||
/* deallocate kernel resources */
|
/* deallocate kernel resources */
|
||||||
|
|
|
@ -214,11 +214,11 @@ typedef union {
|
||||||
|
|
||||||
#define RADEON_NR_SAREA_CLIPRECTS 12
|
#define RADEON_NR_SAREA_CLIPRECTS 12
|
||||||
|
|
||||||
/* There are 2 heaps (local/AGP). Each region within a heap is a
|
/* There are 2 heaps (local/GART). Each region within a heap is a
|
||||||
* minimum of 64k, and there are at most 64 of them per heap.
|
* minimum of 64k, and there are at most 64 of them per heap.
|
||||||
*/
|
*/
|
||||||
#define RADEON_LOCAL_TEX_HEAP 0
|
#define RADEON_LOCAL_TEX_HEAP 0
|
||||||
#define RADEON_AGP_TEX_HEAP 1
|
#define RADEON_GART_TEX_HEAP 1
|
||||||
#define RADEON_NR_TEX_HEAPS 2
|
#define RADEON_NR_TEX_HEAPS 2
|
||||||
#define RADEON_NR_TEX_REGIONS 64
|
#define RADEON_NR_TEX_REGIONS 64
|
||||||
#define RADEON_LOG_TEX_GRANULARITY 16
|
#define RADEON_LOG_TEX_GRANULARITY 16
|
||||||
|
@ -400,7 +400,7 @@ typedef struct drm_radeon_init {
|
||||||
unsigned long sarea_priv_offset;
|
unsigned long sarea_priv_offset;
|
||||||
int is_pci;
|
int is_pci;
|
||||||
int cp_mode;
|
int cp_mode;
|
||||||
int agp_size;
|
int gart_size;
|
||||||
int ring_size;
|
int ring_size;
|
||||||
int usec_timeout;
|
int usec_timeout;
|
||||||
|
|
||||||
|
@ -415,7 +415,7 @@ typedef struct drm_radeon_init {
|
||||||
unsigned long ring_offset;
|
unsigned long ring_offset;
|
||||||
unsigned long ring_rptr_offset;
|
unsigned long ring_rptr_offset;
|
||||||
unsigned long buffers_offset;
|
unsigned long buffers_offset;
|
||||||
unsigned long agp_textures_offset;
|
unsigned long gart_textures_offset;
|
||||||
} drm_radeon_init_t;
|
} drm_radeon_init_t;
|
||||||
|
|
||||||
typedef struct drm_radeon_cp_stop {
|
typedef struct drm_radeon_cp_stop {
|
||||||
|
@ -525,18 +525,18 @@ typedef struct drm_radeon_indirect {
|
||||||
/* 1.3: An ioctl to get parameters that aren't available to the 3d
|
/* 1.3: An ioctl to get parameters that aren't available to the 3d
|
||||||
* client any other way.
|
* client any other way.
|
||||||
*/
|
*/
|
||||||
#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */
|
#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
|
||||||
#define RADEON_PARAM_LAST_FRAME 2
|
#define RADEON_PARAM_LAST_FRAME 2
|
||||||
#define RADEON_PARAM_LAST_DISPATCH 3
|
#define RADEON_PARAM_LAST_DISPATCH 3
|
||||||
#define RADEON_PARAM_LAST_CLEAR 4
|
#define RADEON_PARAM_LAST_CLEAR 4
|
||||||
/* Added with DRM version 1.6. */
|
/* Added with DRM version 1.6. */
|
||||||
#define RADEON_PARAM_IRQ_NR 5
|
#define RADEON_PARAM_IRQ_NR 5
|
||||||
#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */
|
#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
|
||||||
/* Added with DRM version 1.8. */
|
/* Added with DRM version 1.8. */
|
||||||
#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
|
#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
|
||||||
#define RADEON_PARAM_STATUS_HANDLE 8
|
#define RADEON_PARAM_STATUS_HANDLE 8
|
||||||
#define RADEON_PARAM_SAREA_HANDLE 9
|
#define RADEON_PARAM_SAREA_HANDLE 9
|
||||||
#define RADEON_PARAM_AGP_TEX_HANDLE 10
|
#define RADEON_PARAM_GART_TEX_HANDLE 10
|
||||||
|
|
||||||
typedef struct drm_radeon_getparam {
|
typedef struct drm_radeon_getparam {
|
||||||
int param;
|
int param;
|
||||||
|
@ -545,14 +545,14 @@ typedef struct drm_radeon_getparam {
|
||||||
|
|
||||||
/* 1.6: Set up a memory manager for regions of shared memory:
|
/* 1.6: Set up a memory manager for regions of shared memory:
|
||||||
*/
|
*/
|
||||||
#define RADEON_MEM_REGION_AGP 1
|
#define RADEON_MEM_REGION_GART 1
|
||||||
#define RADEON_MEM_REGION_FB 2
|
#define RADEON_MEM_REGION_FB 2
|
||||||
|
|
||||||
typedef struct drm_radeon_mem_alloc {
|
typedef struct drm_radeon_mem_alloc {
|
||||||
int region;
|
int region;
|
||||||
int alignment;
|
int alignment;
|
||||||
int size;
|
int size;
|
||||||
int *region_offset; /* offset from start of fb or agp */
|
int *region_offset; /* offset from start of fb or GART */
|
||||||
} drm_radeon_mem_alloc_t;
|
} drm_radeon_mem_alloc_t;
|
||||||
|
|
||||||
typedef struct drm_radeon_mem_free {
|
typedef struct drm_radeon_mem_free {
|
||||||
|
|
|
@ -73,9 +73,9 @@ typedef struct drm_radeon_private {
|
||||||
drm_radeon_ring_buffer_t ring;
|
drm_radeon_ring_buffer_t ring;
|
||||||
drm_radeon_sarea_t *sarea_priv;
|
drm_radeon_sarea_t *sarea_priv;
|
||||||
|
|
||||||
int agp_size;
|
int gart_size;
|
||||||
u32 agp_vm_start;
|
u32 gart_vm_start;
|
||||||
unsigned long agp_buffers_offset;
|
unsigned long gart_buffers_offset;
|
||||||
|
|
||||||
int cp_mode;
|
int cp_mode;
|
||||||
int cp_running;
|
int cp_running;
|
||||||
|
@ -130,7 +130,7 @@ typedef struct drm_radeon_private {
|
||||||
unsigned long ring_offset;
|
unsigned long ring_offset;
|
||||||
unsigned long ring_rptr_offset;
|
unsigned long ring_rptr_offset;
|
||||||
unsigned long buffers_offset;
|
unsigned long buffers_offset;
|
||||||
unsigned long agp_textures_offset;
|
unsigned long gart_textures_offset;
|
||||||
|
|
||||||
drm_local_map_t *sarea;
|
drm_local_map_t *sarea;
|
||||||
drm_local_map_t *fb;
|
drm_local_map_t *fb;
|
||||||
|
@ -138,9 +138,9 @@ typedef struct drm_radeon_private {
|
||||||
drm_local_map_t *cp_ring;
|
drm_local_map_t *cp_ring;
|
||||||
drm_local_map_t *ring_rptr;
|
drm_local_map_t *ring_rptr;
|
||||||
drm_local_map_t *buffers;
|
drm_local_map_t *buffers;
|
||||||
drm_local_map_t *agp_textures;
|
drm_local_map_t *gart_textures;
|
||||||
|
|
||||||
struct mem_block *agp_heap;
|
struct mem_block *gart_heap;
|
||||||
struct mem_block *fb_heap;
|
struct mem_block *fb_heap;
|
||||||
|
|
||||||
/* SW interrupt */
|
/* SW interrupt */
|
||||||
|
|
|
@ -1,4 +1,4 @@
|
||||||
/* radeon_mem.c -- Simple agp/fb memory manager for radeon -*- linux-c -*-
|
/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*-
|
||||||
*
|
*
|
||||||
* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
|
* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
|
||||||
*
|
*
|
||||||
|
@ -35,7 +35,7 @@
|
||||||
#include "radeon_drm.h"
|
#include "radeon_drm.h"
|
||||||
#include "radeon_drv.h"
|
#include "radeon_drv.h"
|
||||||
|
|
||||||
/* Very simple allocator for agp memory, working on a static range
|
/* Very simple allocator for GART memory, working on a static range
|
||||||
* already mapped into each client's address space.
|
* already mapped into each client's address space.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
@ -212,8 +212,8 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv,
|
||||||
int region )
|
int region )
|
||||||
{
|
{
|
||||||
switch( region ) {
|
switch( region ) {
|
||||||
case RADEON_MEM_REGION_AGP:
|
case RADEON_MEM_REGION_GART:
|
||||||
return &dev_priv->agp_heap;
|
return &dev_priv->gart_heap;
|
||||||
case RADEON_MEM_REGION_FB:
|
case RADEON_MEM_REGION_FB:
|
||||||
return &dev_priv->fb_heap;
|
return &dev_priv->fb_heap;
|
||||||
default:
|
default:
|
||||||
|
|
|
@ -893,7 +893,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
|
||||||
{
|
{
|
||||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||||
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||||
int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
|
int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
|
||||||
int numverts = (int)prim->numverts;
|
int numverts = (int)prim->numverts;
|
||||||
int nbox = sarea_priv->nbox;
|
int nbox = sarea_priv->nbox;
|
||||||
int i = 0;
|
int i = 0;
|
||||||
|
@ -966,7 +966,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
|
||||||
buf->idx, start, end );
|
buf->idx, start, end );
|
||||||
|
|
||||||
if ( start != end ) {
|
if ( start != end ) {
|
||||||
int offset = (dev_priv->agp_buffers_offset
|
int offset = (dev_priv->gart_buffers_offset
|
||||||
+ buf->offset + start);
|
+ buf->offset + start);
|
||||||
int dwords = (end - start + 3) / sizeof(u32);
|
int dwords = (end - start + 3) / sizeof(u32);
|
||||||
|
|
||||||
|
@ -999,7 +999,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
|
||||||
{
|
{
|
||||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||||
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||||
int offset = dev_priv->agp_buffers_offset + prim->offset;
|
int offset = dev_priv->gart_buffers_offset + prim->offset;
|
||||||
u32 *data;
|
u32 *data;
|
||||||
int dwords;
|
int dwords;
|
||||||
int i = 0;
|
int i = 0;
|
||||||
|
@ -2159,8 +2159,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
|
||||||
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
|
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
|
||||||
|
|
||||||
switch( param.param ) {
|
switch( param.param ) {
|
||||||
case RADEON_PARAM_AGP_BUFFER_OFFSET:
|
case RADEON_PARAM_GART_BUFFER_OFFSET:
|
||||||
value = dev_priv->agp_buffers_offset;
|
value = dev_priv->gart_buffers_offset;
|
||||||
break;
|
break;
|
||||||
case RADEON_PARAM_LAST_FRAME:
|
case RADEON_PARAM_LAST_FRAME:
|
||||||
dev_priv->stats.last_frame_reads++;
|
dev_priv->stats.last_frame_reads++;
|
||||||
|
@ -2176,8 +2176,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
|
||||||
case RADEON_PARAM_IRQ_NR:
|
case RADEON_PARAM_IRQ_NR:
|
||||||
value = dev->irq;
|
value = dev->irq;
|
||||||
break;
|
break;
|
||||||
case RADEON_PARAM_AGP_BASE:
|
case RADEON_PARAM_GART_BASE:
|
||||||
value = dev_priv->agp_vm_start;
|
value = dev_priv->gart_vm_start;
|
||||||
break;
|
break;
|
||||||
case RADEON_PARAM_REGISTER_HANDLE:
|
case RADEON_PARAM_REGISTER_HANDLE:
|
||||||
value = dev_priv->mmio_offset;
|
value = dev_priv->mmio_offset;
|
||||||
|
@ -2189,8 +2189,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
|
||||||
/* The lock is the first dword in the sarea. */
|
/* The lock is the first dword in the sarea. */
|
||||||
value = (int)dev->lock.hw_lock;
|
value = (int)dev->lock.hw_lock;
|
||||||
break;
|
break;
|
||||||
case RADEON_PARAM_AGP_TEX_HANDLE:
|
case RADEON_PARAM_GART_TEX_HANDLE:
|
||||||
value = dev_priv->agp_textures_offset;
|
value = dev_priv->gart_textures_offset;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return DRM_ERR(EINVAL);
|
return DRM_ERR(EINVAL);
|
||||||
|
|
Loading…
Reference in New Issue