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Remove artificial PCI GART limitations, rename AGP to GART where 

appropriate
main
Michel Daenzer 2003-08-26 15:44:01 +00:00
parent 963ad33cb6
commit 062751ac47
11 changed files with 128 additions and 134 deletions
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69
shared-core/radeon_cp.c
View File

@ -855,25 +855,23 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
/* Initialize the memory controller */
RADEON_WRITE( RADEON_MC_FB_LOCATION,
(dev_priv->agp_vm_start - 1) & 0xffff0000 );
if ( !dev_priv->is_pci ) {
RADEON_WRITE( RADEON_MC_AGP_LOCATION,
(((dev_priv->agp_vm_start - 1 +
dev_priv->agp_size) & 0xffff0000) |
(dev_priv->agp_vm_start >> 16)) );
}
(dev_priv->gart_vm_start - 1) & 0xffff0000 );
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci )
if ( !dev_priv->is_pci ) {
RADEON_WRITE( RADEON_MC_AGP_LOCATION,
(((dev_priv->gart_vm_start - 1 +
dev_priv->gart_size) & 0xffff0000) |
(dev_priv->gart_vm_start >> 16)) );
ring_start = (dev_priv->cp_ring->offset
- dev->agp->base
+ dev_priv->agp_vm_start);
else
+ dev_priv->gart_vm_start);
} else
#endif
ring_start = (dev_priv->cp_ring->offset
- dev->sg->handle
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
@ -891,7 +889,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
dev_priv->ring_rptr->offset
- dev->agp->base
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
} else
#endif
{
@ -989,11 +987,11 @@ static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
/* set address range for PCI address translate
*/
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
+ dev_priv->agp_size - 1);
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
+ dev_priv->gart_size - 1);
/* Turn off AGP aperture -- is this required for PCIGART?
/* Turn off AGP aperture -- is this required for PCI GART?
*/
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
@ -1117,7 +1115,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
dev_priv->ring_offset = init->ring_offset;
dev_priv->ring_rptr_offset = init->ring_rptr_offset;
dev_priv->buffers_offset = init->buffers_offset;
dev_priv->agp_textures_offset = init->agp_textures_offset;
dev_priv->gart_textures_offset = init->gart_textures_offset;
if(!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
@ -1162,11 +1160,10 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
return DRM_ERR(EINVAL);
}
if ( !dev_priv->is_pci ) {
DRM_FIND_MAP( dev_priv->agp_textures,
init->agp_textures_offset );
if(!dev_priv->agp_textures) {
DRM_ERROR("could not find agp texture region!\n");
if ( init->gart_textures_offset ) {
DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset );
if ( !dev_priv->gart_textures ) {
DRM_ERROR("could not find GART texture region!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
@ -1208,25 +1205,25 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
}
dev_priv->agp_size = init->agp_size;
dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
dev_priv->gart_size = init->gart_size;
dev_priv->gart_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci )
dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
- dev->agp->base
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
else
#endif
dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
- dev->sg->handle
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
DRM_DEBUG( "dev_priv->agp_size %d\n",
dev_priv->agp_size );
DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
dev_priv->agp_vm_start );
DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
dev_priv->agp_buffers_offset );
DRM_DEBUG( "dev_priv->gart_size %d\n",
dev_priv->gart_size );
DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
dev_priv->gart_vm_start );
DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
dev_priv->gart_buffers_offset );
dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
@ -1463,7 +1460,7 @@ void radeon_do_release( drm_device_t *dev )
RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
/* Free memory heap structures */
radeon_mem_takedown( &(dev_priv->agp_heap) );
radeon_mem_takedown( &(dev_priv->gart_heap) );
radeon_mem_takedown( &(dev_priv->fb_heap) );
/* deallocate kernel resources */

20
shared-core/radeon_drm.h
View File

@ -214,11 +214,11 @@ typedef union {
#define RADEON_NR_SAREA_CLIPRECTS 12
/* There are 2 heaps (local/AGP). Each region within a heap is a
/* There are 2 heaps (local/GART). Each region within a heap is a
* minimum of 64k, and there are at most 64 of them per heap.
*/
#define RADEON_LOCAL_TEX_HEAP 0
#define RADEON_AGP_TEX_HEAP 1
#define RADEON_GART_TEX_HEAP 1
#define RADEON_NR_TEX_HEAPS 2
#define RADEON_NR_TEX_REGIONS 64
#define RADEON_LOG_TEX_GRANULARITY 16
@ -400,7 +400,7 @@ typedef struct drm_radeon_init {
unsigned long sarea_priv_offset;
int is_pci;
int cp_mode;
int agp_size;
int gart_size;
int ring_size;
int usec_timeout;
@ -415,7 +415,7 @@ typedef struct drm_radeon_init {
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
unsigned long agp_textures_offset;
unsigned long gart_textures_offset;
} drm_radeon_init_t;
typedef struct drm_radeon_cp_stop {
@ -525,18 +525,18 @@ typedef struct drm_radeon_indirect {
/* 1.3: An ioctl to get parameters that aren't available to the 3d
* client any other way.
*/
#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */
#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
#define RADEON_PARAM_LAST_FRAME 2
#define RADEON_PARAM_LAST_DISPATCH 3
#define RADEON_PARAM_LAST_CLEAR 4
/* Added with DRM version 1.6. */
#define RADEON_PARAM_IRQ_NR 5
#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */
#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
/* Added with DRM version 1.8. */
#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
#define RADEON_PARAM_STATUS_HANDLE 8
#define RADEON_PARAM_SAREA_HANDLE 9
#define RADEON_PARAM_AGP_TEX_HANDLE 10
#define RADEON_PARAM_GART_TEX_HANDLE 10
typedef struct drm_radeon_getparam {
int param;
@ -545,14 +545,14 @@ typedef struct drm_radeon_getparam {
/* 1.6: Set up a memory manager for regions of shared memory:
*/
#define RADEON_MEM_REGION_AGP 1
#define RADEON_MEM_REGION_FB 2
#define RADEON_MEM_REGION_GART 1
#define RADEON_MEM_REGION_FB 2
typedef struct drm_radeon_mem_alloc {
int region;
int alignment;
int size;
int *region_offset; /* offset from start of fb or agp */
int *region_offset; /* offset from start of fb or GART */
} drm_radeon_mem_alloc_t;
typedef struct drm_radeon_mem_free {

12
shared-core/radeon_drv.h
View File

@ -73,9 +73,9 @@ typedef struct drm_radeon_private {
drm_radeon_ring_buffer_t ring;
drm_radeon_sarea_t *sarea_priv;
int agp_size;
u32 agp_vm_start;
unsigned long agp_buffers_offset;
int gart_size;
u32 gart_vm_start;
unsigned long gart_buffers_offset;
int cp_mode;
int cp_running;
@ -130,7 +130,7 @@ typedef struct drm_radeon_private {
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
unsigned long agp_textures_offset;
unsigned long gart_textures_offset;
drm_local_map_t *sarea;
drm_local_map_t *fb;
@ -138,9 +138,9 @@ typedef struct drm_radeon_private {
drm_local_map_t *cp_ring;
drm_local_map_t *ring_rptr;
drm_local_map_t *buffers;
drm_local_map_t *agp_textures;
drm_local_map_t *gart_textures;
struct mem_block *agp_heap;
struct mem_block *gart_heap;
struct mem_block *fb_heap;
/* SW interrupt */

8
shared-core/radeon_mem.c
View File

@ -1,4 +1,4 @@
/* radeon_mem.c -- Simple agp/fb memory manager for radeon -*- linux-c -*-
/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*-
*
* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
*
@ -35,7 +35,7 @@
#include "radeon_drm.h"
#include "radeon_drv.h"
/* Very simple allocator for agp memory, working on a static range
/* Very simple allocator for GART memory, working on a static range
* already mapped into each client's address space.
*/
@ -212,8 +212,8 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv,
int region )
{
switch( region ) {
case RADEON_MEM_REGION_AGP:
return &dev_priv->agp_heap;
case RADEON_MEM_REGION_GART:
return &dev_priv->gart_heap;
case RADEON_MEM_REGION_FB:
return &dev_priv->fb_heap;
default:

18
shared-core/radeon_state.c
View File

@ -893,7 +893,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
int numverts = (int)prim->numverts;
int nbox = sarea_priv->nbox;
int i = 0;
@ -966,7 +966,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
buf->idx, start, end );
if ( start != end ) {
int offset = (dev_priv->agp_buffers_offset
int offset = (dev_priv->gart_buffers_offset
+ buf->offset + start);
int dwords = (end - start + 3) / sizeof(u32);
@ -999,7 +999,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + prim->offset;
int offset = dev_priv->gart_buffers_offset + prim->offset;
u32 *data;
int dwords;
int i = 0;
@ -2159,8 +2159,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
switch( param.param ) {
case RADEON_PARAM_AGP_BUFFER_OFFSET:
value = dev_priv->agp_buffers_offset;
case RADEON_PARAM_GART_BUFFER_OFFSET:
value = dev_priv->gart_buffers_offset;
break;
case RADEON_PARAM_LAST_FRAME:
dev_priv->stats.last_frame_reads++;
@ -2176,8 +2176,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
case RADEON_PARAM_IRQ_NR:
value = dev->irq;
break;
case RADEON_PARAM_AGP_BASE:
value = dev_priv->agp_vm_start;
case RADEON_PARAM_GART_BASE:
value = dev_priv->gart_vm_start;
break;
case RADEON_PARAM_REGISTER_HANDLE:
value = dev_priv->mmio_offset;
@ -2189,8 +2189,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
/* The lock is the first dword in the sarea. */
value = (int)dev->lock.hw_lock;
break;
case RADEON_PARAM_AGP_TEX_HANDLE:
value = dev_priv->agp_textures_offset;
case RADEON_PARAM_GART_TEX_HANDLE:
value = dev_priv->gart_textures_offset;
break;
default:
return DRM_ERR(EINVAL);

8
shared/radeon.h
View File

@ -68,11 +68,11 @@
* 1.5 - Add r200 packets to cmdbuf ioctl
* - Add r200 function to init ioctl
* - Add 'scalar2' instruction to cmdbuf
* 1.6 - Add static agp memory manager
* 1.6 - Add static GART memory manager
* Add irq handler (won't be turned on unless X server knows to)
* Add irq ioctls and irq_active getparam.
* Add wait command for cmdbuf ioctl
* Add agp offset query for getparam
* Add GART offset query for getparam
* 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
* and R200_PP_CUBIC_OFFSET_F1_[0..5].
* Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
@ -113,7 +113,7 @@
/* When a client dies:
* - Check for and clean up flipped page state
* - Free any alloced agp memory.
* - Free any alloced GART memory.
*
* DRM infrastructure takes care of reclaiming dma buffers.
*/
@ -124,7 +124,7 @@ do { \
if ( dev_priv->page_flipping ) { \
radeon_do_cleanup_pageflip( dev ); \
} \
radeon_mem_release( filp, dev_priv->agp_heap ); \
radeon_mem_release( filp, dev_priv->gart_heap ); \
radeon_mem_release( filp, dev_priv->fb_heap ); \
} \
} while (0)

69
shared/radeon_cp.c
View File

@ -855,25 +855,23 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
/* Initialize the memory controller */
RADEON_WRITE( RADEON_MC_FB_LOCATION,
(dev_priv->agp_vm_start - 1) & 0xffff0000 );
if ( !dev_priv->is_pci ) {
RADEON_WRITE( RADEON_MC_AGP_LOCATION,
(((dev_priv->agp_vm_start - 1 +
dev_priv->agp_size) & 0xffff0000) |
(dev_priv->agp_vm_start >> 16)) );
}
(dev_priv->gart_vm_start - 1) & 0xffff0000 );
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci )
if ( !dev_priv->is_pci ) {
RADEON_WRITE( RADEON_MC_AGP_LOCATION,
(((dev_priv->gart_vm_start - 1 +
dev_priv->gart_size) & 0xffff0000) |
(dev_priv->gart_vm_start >> 16)) );
ring_start = (dev_priv->cp_ring->offset
- dev->agp->base
+ dev_priv->agp_vm_start);
else
+ dev_priv->gart_vm_start);
} else
#endif
ring_start = (dev_priv->cp_ring->offset
- dev->sg->handle
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
@ -891,7 +889,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
dev_priv->ring_rptr->offset
- dev->agp->base
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
} else
#endif
{
@ -989,11 +987,11 @@ static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
/* set address range for PCI address translate
*/
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
+ dev_priv->agp_size - 1);
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
+ dev_priv->gart_size - 1);
/* Turn off AGP aperture -- is this required for PCIGART?
/* Turn off AGP aperture -- is this required for PCI GART?
*/
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
@ -1117,7 +1115,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
dev_priv->ring_offset = init->ring_offset;
dev_priv->ring_rptr_offset = init->ring_rptr_offset;
dev_priv->buffers_offset = init->buffers_offset;
dev_priv->agp_textures_offset = init->agp_textures_offset;
dev_priv->gart_textures_offset = init->gart_textures_offset;
if(!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
@ -1162,11 +1160,10 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
return DRM_ERR(EINVAL);
}
if ( !dev_priv->is_pci ) {
DRM_FIND_MAP( dev_priv->agp_textures,
init->agp_textures_offset );
if(!dev_priv->agp_textures) {
DRM_ERROR("could not find agp texture region!\n");
if ( init->gart_textures_offset ) {
DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset );
if ( !dev_priv->gart_textures ) {
DRM_ERROR("could not find GART texture region!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
@ -1208,25 +1205,25 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
}
dev_priv->agp_size = init->agp_size;
dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
dev_priv->gart_size = init->gart_size;
dev_priv->gart_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci )
dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
- dev->agp->base
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
else
#endif
dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
- dev->sg->handle
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
DRM_DEBUG( "dev_priv->agp_size %d\n",
dev_priv->agp_size );
DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
dev_priv->agp_vm_start );
DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
dev_priv->agp_buffers_offset );
DRM_DEBUG( "dev_priv->gart_size %d\n",
dev_priv->gart_size );
DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
dev_priv->gart_vm_start );
DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
dev_priv->gart_buffers_offset );
dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
@ -1463,7 +1460,7 @@ void radeon_do_release( drm_device_t *dev )
RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
/* Free memory heap structures */
radeon_mem_takedown( &(dev_priv->agp_heap) );
radeon_mem_takedown( &(dev_priv->gart_heap) );
radeon_mem_takedown( &(dev_priv->fb_heap) );
/* deallocate kernel resources */

20
shared/radeon_drm.h
View File

@ -214,11 +214,11 @@ typedef union {
#define RADEON_NR_SAREA_CLIPRECTS 12
/* There are 2 heaps (local/AGP). Each region within a heap is a
/* There are 2 heaps (local/GART). Each region within a heap is a
* minimum of 64k, and there are at most 64 of them per heap.
*/
#define RADEON_LOCAL_TEX_HEAP 0
#define RADEON_AGP_TEX_HEAP 1
#define RADEON_GART_TEX_HEAP 1
#define RADEON_NR_TEX_HEAPS 2
#define RADEON_NR_TEX_REGIONS 64
#define RADEON_LOG_TEX_GRANULARITY 16
@ -400,7 +400,7 @@ typedef struct drm_radeon_init {
unsigned long sarea_priv_offset;
int is_pci;
int cp_mode;
int agp_size;
int gart_size;
int ring_size;
int usec_timeout;
@ -415,7 +415,7 @@ typedef struct drm_radeon_init {
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
unsigned long agp_textures_offset;
unsigned long gart_textures_offset;
} drm_radeon_init_t;
typedef struct drm_radeon_cp_stop {
@ -525,18 +525,18 @@ typedef struct drm_radeon_indirect {
/* 1.3: An ioctl to get parameters that aren't available to the 3d
* client any other way.
*/
#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */
#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
#define RADEON_PARAM_LAST_FRAME 2
#define RADEON_PARAM_LAST_DISPATCH 3
#define RADEON_PARAM_LAST_CLEAR 4
/* Added with DRM version 1.6. */
#define RADEON_PARAM_IRQ_NR 5
#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */
#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
/* Added with DRM version 1.8. */
#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
#define RADEON_PARAM_STATUS_HANDLE 8
#define RADEON_PARAM_SAREA_HANDLE 9
#define RADEON_PARAM_AGP_TEX_HANDLE 10
#define RADEON_PARAM_GART_TEX_HANDLE 10
typedef struct drm_radeon_getparam {
int param;
@ -545,14 +545,14 @@ typedef struct drm_radeon_getparam {
/* 1.6: Set up a memory manager for regions of shared memory:
*/
#define RADEON_MEM_REGION_AGP 1
#define RADEON_MEM_REGION_FB 2
#define RADEON_MEM_REGION_GART 1
#define RADEON_MEM_REGION_FB 2
typedef struct drm_radeon_mem_alloc {
int region;
int alignment;
int size;
int *region_offset; /* offset from start of fb or agp */
int *region_offset; /* offset from start of fb or GART */
} drm_radeon_mem_alloc_t;
typedef struct drm_radeon_mem_free {

12
shared/radeon_drv.h
View File

@ -73,9 +73,9 @@ typedef struct drm_radeon_private {
drm_radeon_ring_buffer_t ring;
drm_radeon_sarea_t *sarea_priv;
int agp_size;
u32 agp_vm_start;
unsigned long agp_buffers_offset;
int gart_size;
u32 gart_vm_start;
unsigned long gart_buffers_offset;
int cp_mode;
int cp_running;
@ -130,7 +130,7 @@ typedef struct drm_radeon_private {
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
unsigned long agp_textures_offset;
unsigned long gart_textures_offset;
drm_local_map_t *sarea;
drm_local_map_t *fb;
@ -138,9 +138,9 @@ typedef struct drm_radeon_private {
drm_local_map_t *cp_ring;
drm_local_map_t *ring_rptr;
drm_local_map_t *buffers;
drm_local_map_t *agp_textures;
drm_local_map_t *gart_textures;
struct mem_block *agp_heap;
struct mem_block *gart_heap;
struct mem_block *fb_heap;
/* SW interrupt */

8
shared/radeon_mem.c
View File

@ -1,4 +1,4 @@
/* radeon_mem.c -- Simple agp/fb memory manager for radeon -*- linux-c -*-
/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*-
*
* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
*
@ -35,7 +35,7 @@
#include "radeon_drm.h"
#include "radeon_drv.h"
/* Very simple allocator for agp memory, working on a static range
/* Very simple allocator for GART memory, working on a static range
* already mapped into each client's address space.
*/
@ -212,8 +212,8 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv,
int region )
{
switch( region ) {
case RADEON_MEM_REGION_AGP:
return &dev_priv->agp_heap;
case RADEON_MEM_REGION_GART:
return &dev_priv->gart_heap;
case RADEON_MEM_REGION_FB:
return &dev_priv->fb_heap;
default:

18
shared/radeon_state.c
View File

@ -893,7 +893,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
int numverts = (int)prim->numverts;
int nbox = sarea_priv->nbox;
int i = 0;
@ -966,7 +966,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
buf->idx, start, end );
if ( start != end ) {
int offset = (dev_priv->agp_buffers_offset
int offset = (dev_priv->gart_buffers_offset
+ buf->offset + start);
int dwords = (end - start + 3) / sizeof(u32);
@ -999,7 +999,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + prim->offset;
int offset = dev_priv->gart_buffers_offset + prim->offset;
u32 *data;
int dwords;
int i = 0;
@ -2159,8 +2159,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
switch( param.param ) {
case RADEON_PARAM_AGP_BUFFER_OFFSET:
value = dev_priv->agp_buffers_offset;
case RADEON_PARAM_GART_BUFFER_OFFSET:
value = dev_priv->gart_buffers_offset;
break;
case RADEON_PARAM_LAST_FRAME:
dev_priv->stats.last_frame_reads++;
@ -2176,8 +2176,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
case RADEON_PARAM_IRQ_NR:
value = dev->irq;
break;
case RADEON_PARAM_AGP_BASE:
value = dev_priv->agp_vm_start;
case RADEON_PARAM_GART_BASE:
value = dev_priv->gart_vm_start;
break;
case RADEON_PARAM_REGISTER_HANDLE:
value = dev_priv->mmio_offset;
@ -2189,8 +2189,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
/* The lock is the first dword in the sarea. */
value = (int)dev->lock.hw_lock;
break;
case RADEON_PARAM_AGP_TEX_HANDLE:
value = dev_priv->agp_textures_offset;
case RADEON_PARAM_GART_TEX_HANDLE:
value = dev_priv->gart_textures_offset;
break;
default:
return DRM_ERR(EINVAL);