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Cleanup gen2 tiling confusion 

A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter 2011-03-26 15:04:04 +01:00
parent fd3ed34a20
commit 06ebbf7c2c
1 changed files with 3 additions and 4 deletions
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7
intel/intel_bufmgr_gem.c
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@ -762,13 +762,12 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
aligned_y = y;
height_alignment = 2;
if (tiling == I915_TILING_X)
if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
height_alignment = 16;
else if (tiling == I915_TILING_X)
height_alignment = 8;
else if (tiling == I915_TILING_Y)
height_alignment = 32;
/* i8xx has a interleaved 2-row tile layout */
if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
height_alignment *= 2;
aligned_y = ALIGN(y, height_alignment);
stride = x * cpp;