Clean up Radeon DRI resume code
Michel Daenzer
parent
0f094c33da
commit
07a9b30082
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@ -975,10 +975,36 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
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RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
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}
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/* Enable or disable PCI GART on the chip */
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static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
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{
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u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
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if ( on ) {
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RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
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/* set PCI GART page-table base address
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*/
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RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
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/* set address range for PCI address translate
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*/
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RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
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RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
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+ dev_priv->agp_size - 1);
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/* Turn off AGP aperture -- is this required for PCIGART?
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*/
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RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
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RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
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} else {
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RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
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}
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}
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static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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{
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drm_radeon_private_t *dev_priv;
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u32 tmp;
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DRM_DEBUG( "\n" );
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dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
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@ -1213,7 +1239,13 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
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if ( dev_priv->is_pci ) {
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#if __REALLY_HAVE_AGP
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if ( !dev_priv->is_pci ) {
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/* Turn off PCI GART */
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radeon_set_pcigart( dev_priv, 0 );
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} else
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#endif
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{
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if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
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&dev_priv->bus_pci_gart)) {
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DRM_ERROR( "failed to init PCI GART!\n" );
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@ -1221,32 +1253,9 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(ENOMEM);
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}
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/* Turn on PCI GART
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*/
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tmp = RADEON_READ( RADEON_AIC_CNTL )
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| RADEON_PCIGART_TRANSLATE_EN;
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RADEON_WRITE( RADEON_AIC_CNTL, tmp );
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/* set PCI GART page-table base address
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*/
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RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
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/* set address range for PCI address translate
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*/
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RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
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RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
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+ dev_priv->agp_size - 1);
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/* Turn off AGP aperture -- is this required for PCIGART?
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*/
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RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
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RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
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} else {
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/* Turn off PCI GART
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*/
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tmp = RADEON_READ( RADEON_AIC_CNTL )
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& ~RADEON_PCIGART_TRANSLATE_EN;
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RADEON_WRITE( RADEON_AIC_CNTL, tmp );
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/* Turn on PCI GART */
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radeon_set_pcigart( dev_priv, 1 );
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}
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radeon_cp_load_microcode( dev_priv );
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@ -1304,162 +1313,30 @@ int radeon_do_cleanup_cp( drm_device_t *dev )
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/* This code will reinit the Radeon CP hardware after a resume from disc.
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* AFAIK, it would be very difficult to pickle the state at suspend time, so
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* here we make sure that all Radeon hardware initialisation is re-done without
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* affecting running applications. This function is called radeon_do_resume_cp()
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* as it was derived from radeon_init_cp, where most of the initialisation takes
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* place during DRI init.
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*
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* This patch is NOT to be confused with my and Michel Daenzer's earlier DRI
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* reinit work, which de- and re-initialised the complete DRI at every VT
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* switch.
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* affecting running applications.
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*
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* Charl P. Botha <http://cpbotha.net>
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*/
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static int radeon_do_resume_cp( drm_device_t *dev)
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static int radeon_do_resume_cp( drm_device_t *dev )
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{
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drm_radeon_private_t *dev_priv;
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u32 tmp;
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DRM_DEBUG( "\n" );
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if ( !dev_priv ) {
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DRM_ERROR( "Called with no initialization\n" );
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return DRM_ERR( EINVAL );
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}
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DRM_DEBUG("Starting radeon_do_resume_cp()\n");
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/* get the existing dev_private */
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dev_priv = dev->dev_private;
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#if !defined(PCIGART_ENABLED)
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/* PCI support is not 100% working, so we disable it here.
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*/
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if ( dev_priv->is_pci ) {
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DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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#endif
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if ( dev_priv->is_pci && !dev->sg ) {
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DRM_ERROR( "PCI GART memory not allocated!\n" );
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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if ( dev_priv->usec_timeout < 1 ||
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dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
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DRM_DEBUG( "TIMEOUT problem!\n" );
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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if ( ( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
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( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
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DRM_DEBUG( "BAD cp_mode (%x)!\n", dev_priv->cp_mode );
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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if(!dev_priv->sarea) {
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DRM_ERROR("could not find sarea!\n");
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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if(!dev_priv->fb) {
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DRM_ERROR("could not find framebuffer!\n");
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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if(!dev_priv->mmio) {
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DRM_ERROR("could not find mmio region!\n");
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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if(!dev_priv->cp_ring) {
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DRM_ERROR("could not find cp ring region!\n");
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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if(!dev_priv->ring_rptr) {
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DRM_ERROR("could not find ring read pointer!\n");
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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if(!dev_priv->buffers) {
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DRM_ERROR("could not find dma buffer region!\n");
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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if ( !dev_priv->is_pci ) {
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if(!dev_priv->agp_textures) {
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DRM_ERROR("could not find agp texture region!\n");
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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}
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if ( !dev_priv->is_pci ) {
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if(!dev_priv->cp_ring->handle ||
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!dev_priv->ring_rptr->handle ||
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!dev_priv->buffers->handle) {
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DRM_ERROR("could not find ioremap agp regions!\n");
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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} else {
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DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
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dev_priv->cp_ring->handle );
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DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
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dev_priv->ring_rptr->handle );
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DRM_DEBUG( "dev_priv->buffers->handle %p\n",
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dev_priv->buffers->handle );
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}
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DRM_DEBUG( "dev_priv->agp_size %d\n",
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dev_priv->agp_size );
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DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
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dev_priv->agp_vm_start );
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DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
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dev_priv->agp_buffers_offset );
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#if __REALLY_HAVE_AGP
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if ( !dev_priv->is_pci ) {
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/* Turn off PCI GART
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*/
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tmp = RADEON_READ( RADEON_AIC_CNTL )
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& ~RADEON_PCIGART_TRANSLATE_EN;
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RADEON_WRITE( RADEON_AIC_CNTL, tmp );
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/* Turn off PCI GART */
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radeon_set_pcigart( dev_priv, 0 );
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} else
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#endif
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{
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/* I'm not so sure about this ati_picgart_init after at resume-time... */
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if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
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&dev_priv->bus_pci_gart)) {
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DRM_ERROR( "failed to init PCI GART!\n" );
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(ENOMEM);
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}
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tmp = RADEON_READ( RADEON_AIC_CNTL )
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| RADEON_PCIGART_TRANSLATE_EN;
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RADEON_WRITE( RADEON_AIC_CNTL, tmp );
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/* set PCI GART page-table base address
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*/
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RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
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/* set address range for PCI address translate
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*/
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RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
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RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
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+ dev_priv->agp_size - 1);
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/* Turn off AGP aperture -- is this required for PCIGART?
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*/
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RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
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RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
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/* Turn on PCI GART */
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radeon_set_pcigart( dev_priv, 1 );
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}
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radeon_cp_load_microcode( dev_priv );
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@ -1467,6 +1344,8 @@ static int radeon_do_resume_cp( drm_device_t *dev)
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radeon_do_engine_reset( dev );
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DRM_DEBUG("radeon_do_resume_cp() complete\n");
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return 0;
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}
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@ -79,8 +79,8 @@
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* R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
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* 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
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* Add 'GET' queries for starting additional clients on different VT's.
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* Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
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* 1.9 - Add texture rectangle support for r100.
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* 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
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* Add texture rectangle support for r100.
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*/
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#define DRIVER_IOCTLS \
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[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
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@ -975,10 +975,36 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
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RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
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}
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/* Enable or disable PCI GART on the chip */
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static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
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{
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u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
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if ( on ) {
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RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
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/* set PCI GART page-table base address
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*/
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RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
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/* set address range for PCI address translate
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*/
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RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
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RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
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+ dev_priv->agp_size - 1);
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/* Turn off AGP aperture -- is this required for PCIGART?
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*/
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RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
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RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
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} else {
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RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
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}
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}
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static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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{
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drm_radeon_private_t *dev_priv;
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u32 tmp;
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DRM_DEBUG( "\n" );
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dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
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@ -1213,7 +1239,13 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
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if ( dev_priv->is_pci ) {
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#if __REALLY_HAVE_AGP
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if ( !dev_priv->is_pci ) {
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/* Turn off PCI GART */
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radeon_set_pcigart( dev_priv, 0 );
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} else
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#endif
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{
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if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
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&dev_priv->bus_pci_gart)) {
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DRM_ERROR( "failed to init PCI GART!\n" );
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@ -1221,32 +1253,9 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(ENOMEM);
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}
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/* Turn on PCI GART
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*/
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tmp = RADEON_READ( RADEON_AIC_CNTL )
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| RADEON_PCIGART_TRANSLATE_EN;
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RADEON_WRITE( RADEON_AIC_CNTL, tmp );
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/* set PCI GART page-table base address
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*/
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RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
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/* set address range for PCI address translate
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*/
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RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
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RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
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+ dev_priv->agp_size - 1);
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/* Turn off AGP aperture -- is this required for PCIGART?
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*/
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RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
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RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
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} else {
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/* Turn off PCI GART
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*/
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tmp = RADEON_READ( RADEON_AIC_CNTL )
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& ~RADEON_PCIGART_TRANSLATE_EN;
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RADEON_WRITE( RADEON_AIC_CNTL, tmp );
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/* Turn on PCI GART */
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radeon_set_pcigart( dev_priv, 1 );
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}
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radeon_cp_load_microcode( dev_priv );
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@ -1304,162 +1313,30 @@ int radeon_do_cleanup_cp( drm_device_t *dev )
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/* This code will reinit the Radeon CP hardware after a resume from disc.
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* AFAIK, it would be very difficult to pickle the state at suspend time, so
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* here we make sure that all Radeon hardware initialisation is re-done without
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* affecting running applications. This function is called radeon_do_resume_cp()
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* as it was derived from radeon_init_cp, where most of the initialisation takes
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* place during DRI init.
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*
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* This patch is NOT to be confused with my and Michel Daenzer's earlier DRI
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* reinit work, which de- and re-initialised the complete DRI at every VT
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* switch.
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* affecting running applications.
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*
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* Charl P. Botha <http://cpbotha.net>
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*/
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static int radeon_do_resume_cp( drm_device_t *dev)
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static int radeon_do_resume_cp( drm_device_t *dev )
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{
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drm_radeon_private_t *dev_priv;
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u32 tmp;
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DRM_DEBUG( "\n" );
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if ( !dev_priv ) {
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DRM_ERROR( "Called with no initialization\n" );
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return DRM_ERR( EINVAL );
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}
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DRM_DEBUG("Starting radeon_do_resume_cp()\n");
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/* get the existing dev_private */
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dev_priv = dev->dev_private;
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#if !defined(PCIGART_ENABLED)
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/* PCI support is not 100% working, so we disable it here.
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*/
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if ( dev_priv->is_pci ) {
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DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
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radeon_do_cleanup_cp(dev);
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return DRM_ERR(EINVAL);
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}
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#endif
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||||
|
||||
if ( dev_priv->is_pci && !dev->sg ) {
|
||||
DRM_ERROR( "PCI GART memory not allocated!\n" );
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( dev_priv->usec_timeout < 1 ||
|
||||
dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
|
||||
DRM_DEBUG( "TIMEOUT problem!\n" );
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( ( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
|
||||
( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
|
||||
DRM_DEBUG( "BAD cp_mode (%x)!\n", dev_priv->cp_mode );
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if(!dev_priv->sarea) {
|
||||
DRM_ERROR("could not find sarea!\n");
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if(!dev_priv->fb) {
|
||||
DRM_ERROR("could not find framebuffer!\n");
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if(!dev_priv->mmio) {
|
||||
DRM_ERROR("could not find mmio region!\n");
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if(!dev_priv->cp_ring) {
|
||||
DRM_ERROR("could not find cp ring region!\n");
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if(!dev_priv->ring_rptr) {
|
||||
DRM_ERROR("could not find ring read pointer!\n");
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if(!dev_priv->buffers) {
|
||||
DRM_ERROR("could not find dma buffer region!\n");
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( !dev_priv->is_pci ) {
|
||||
if(!dev_priv->agp_textures) {
|
||||
DRM_ERROR("could not find agp texture region!\n");
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
if ( !dev_priv->is_pci ) {
|
||||
if(!dev_priv->cp_ring->handle ||
|
||||
!dev_priv->ring_rptr->handle ||
|
||||
!dev_priv->buffers->handle) {
|
||||
DRM_ERROR("could not find ioremap agp regions!\n");
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
} else {
|
||||
DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
|
||||
dev_priv->cp_ring->handle );
|
||||
DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
|
||||
dev_priv->ring_rptr->handle );
|
||||
DRM_DEBUG( "dev_priv->buffers->handle %p\n",
|
||||
dev_priv->buffers->handle );
|
||||
}
|
||||
|
||||
|
||||
DRM_DEBUG( "dev_priv->agp_size %d\n",
|
||||
dev_priv->agp_size );
|
||||
DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
|
||||
dev_priv->agp_vm_start );
|
||||
DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
|
||||
dev_priv->agp_buffers_offset );
|
||||
|
||||
#if __REALLY_HAVE_AGP
|
||||
if ( !dev_priv->is_pci ) {
|
||||
/* Turn off PCI GART
|
||||
*/
|
||||
tmp = RADEON_READ( RADEON_AIC_CNTL )
|
||||
& ~RADEON_PCIGART_TRANSLATE_EN;
|
||||
RADEON_WRITE( RADEON_AIC_CNTL, tmp );
|
||||
/* Turn off PCI GART */
|
||||
radeon_set_pcigart( dev_priv, 0 );
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
/* I'm not so sure about this ati_picgart_init after at resume-time... */
|
||||
if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
|
||||
&dev_priv->bus_pci_gart)) {
|
||||
DRM_ERROR( "failed to init PCI GART!\n" );
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(ENOMEM);
|
||||
}
|
||||
|
||||
tmp = RADEON_READ( RADEON_AIC_CNTL )
|
||||
| RADEON_PCIGART_TRANSLATE_EN;
|
||||
RADEON_WRITE( RADEON_AIC_CNTL, tmp );
|
||||
|
||||
/* set PCI GART page-table base address
|
||||
*/
|
||||
RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
|
||||
|
||||
/* set address range for PCI address translate
|
||||
*/
|
||||
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
|
||||
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
|
||||
+ dev_priv->agp_size - 1);
|
||||
|
||||
/* Turn off AGP aperture -- is this required for PCIGART?
|
||||
*/
|
||||
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
|
||||
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
|
||||
/* Turn on PCI GART */
|
||||
radeon_set_pcigart( dev_priv, 1 );
|
||||
}
|
||||
|
||||
radeon_cp_load_microcode( dev_priv );
|
||||
|
|
@ -1467,6 +1344,8 @@ static int radeon_do_resume_cp( drm_device_t *dev)
|
|||
|
||||
radeon_do_engine_reset( dev );
|
||||
|
||||
DRM_DEBUG("radeon_do_resume_cp() complete\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue