intel: Use symbol visibility.
No exports changed for this driver. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>main
Maarten Lankhorst
parent
58ce9d6292
commit
07fead4462
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@ -24,6 +24,7 @@
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AM_CFLAGS = \
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$(WARN_CFLAGS) \
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$(VISIBILITY_CFLAGS) \
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-I$(top_srcdir) \
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-I$(top_srcdir)/intel \
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$(PTHREADSTUBS_CFLAGS) \
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@ -37,6 +37,7 @@
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#include <drm.h>
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#include <i915_drm.h>
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#include <pciaccess.h>
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#include "libdrm.h"
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#include "intel_bufmgr.h"
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#include "intel_bufmgr_priv.h"
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#include "xf86drm.h"
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@ -46,21 +47,21 @@
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* Convenience functions for buffer management methods.
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*/
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drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
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drm_public drm_intel_bo *
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drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
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unsigned long size, unsigned int alignment)
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{
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return bufmgr->bo_alloc(bufmgr, name, size, alignment);
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}
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drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
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const char *name,
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unsigned long size,
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unsigned int alignment)
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drm_public drm_intel_bo *
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drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name,
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unsigned long size, unsigned int alignment)
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{
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return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
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}
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drm_intel_bo *
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drm_public drm_intel_bo *
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drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
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int x, int y, int cpp, uint32_t *tiling_mode,
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unsigned long *pitch, unsigned long flags)
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@ -69,12 +70,14 @@ drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
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tiling_mode, pitch, flags);
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}
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void drm_intel_bo_reference(drm_intel_bo *bo)
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drm_public void
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drm_intel_bo_reference(drm_intel_bo *bo)
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{
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bo->bufmgr->bo_reference(bo);
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}
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void drm_intel_bo_unreference(drm_intel_bo *bo)
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drm_public void
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drm_intel_bo_unreference(drm_intel_bo *bo)
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{
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if (bo == NULL)
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return;
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@ -82,24 +85,26 @@ void drm_intel_bo_unreference(drm_intel_bo *bo)
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bo->bufmgr->bo_unreference(bo);
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}
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int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
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drm_public int
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drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
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{
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return buf->bufmgr->bo_map(buf, write_enable);
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}
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int drm_intel_bo_unmap(drm_intel_bo *buf)
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drm_public int
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drm_intel_bo_unmap(drm_intel_bo *buf)
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{
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return buf->bufmgr->bo_unmap(buf);
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}
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int
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drm_public int
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drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
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unsigned long size, const void *data)
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{
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return bo->bufmgr->bo_subdata(bo, offset, size, data);
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}
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int
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drm_public int
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drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
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unsigned long size, void *data)
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{
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@ -118,24 +123,26 @@ drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
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return 0;
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}
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void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
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drm_public void
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drm_intel_bo_wait_rendering(drm_intel_bo *bo)
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{
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bo->bufmgr->bo_wait_rendering(bo);
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}
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void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
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drm_public void
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drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
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{
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bufmgr->destroy(bufmgr);
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}
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int
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drm_public int
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drm_intel_bo_exec(drm_intel_bo *bo, int used,
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drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
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{
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return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
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}
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int
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drm_public int
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drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
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drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
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unsigned int rings)
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@ -155,17 +162,20 @@ drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
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}
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}
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void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
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drm_public void
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drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
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{
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bufmgr->debug = enable_debug;
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}
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int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
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drm_public int
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drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
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{
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return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
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}
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int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
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drm_public int
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drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
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{
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if (bo->bufmgr->bo_flink)
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return bo->bufmgr->bo_flink(bo, name);
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@ -173,7 +183,7 @@ int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
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return -ENODEV;
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}
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int
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drm_public int
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drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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drm_intel_bo *target_bo, uint32_t target_offset,
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uint32_t read_domains, uint32_t write_domain)
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@ -184,7 +194,7 @@ drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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}
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/* For fence registers, not GL fences */
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int
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drm_public int
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drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
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drm_intel_bo *target_bo, uint32_t target_offset,
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uint32_t read_domains, uint32_t write_domain)
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@ -195,7 +205,8 @@ drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
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}
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int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
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drm_public int
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drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
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{
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if (bo->bufmgr->bo_pin)
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return bo->bufmgr->bo_pin(bo, alignment);
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@ -203,7 +214,8 @@ int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
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return -ENODEV;
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}
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int drm_intel_bo_unpin(drm_intel_bo *bo)
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drm_public int
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drm_intel_bo_unpin(drm_intel_bo *bo)
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{
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if (bo->bufmgr->bo_unpin)
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return bo->bufmgr->bo_unpin(bo);
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@ -211,7 +223,8 @@ int drm_intel_bo_unpin(drm_intel_bo *bo)
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return -ENODEV;
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}
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int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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drm_public int
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drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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uint32_t stride)
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{
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if (bo->bufmgr->bo_set_tiling)
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@ -221,7 +234,8 @@ int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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return 0;
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}
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int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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drm_public int
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drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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uint32_t * swizzle_mode)
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{
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if (bo->bufmgr->bo_get_tiling)
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@ -232,40 +246,46 @@ int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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return 0;
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}
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int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
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drm_public int
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drm_intel_bo_disable_reuse(drm_intel_bo *bo)
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{
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if (bo->bufmgr->bo_disable_reuse)
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return bo->bufmgr->bo_disable_reuse(bo);
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return 0;
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}
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int drm_intel_bo_is_reusable(drm_intel_bo *bo)
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drm_public int
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drm_intel_bo_is_reusable(drm_intel_bo *bo)
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{
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if (bo->bufmgr->bo_is_reusable)
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return bo->bufmgr->bo_is_reusable(bo);
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return 0;
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}
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int drm_intel_bo_busy(drm_intel_bo *bo)
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drm_public int
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drm_intel_bo_busy(drm_intel_bo *bo)
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{
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if (bo->bufmgr->bo_busy)
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return bo->bufmgr->bo_busy(bo);
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return 0;
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}
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int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
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drm_public int
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drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
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{
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if (bo->bufmgr->bo_madvise)
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return bo->bufmgr->bo_madvise(bo, madv);
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return -1;
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}
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int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
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drm_public int
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drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
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{
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return bo->bufmgr->bo_references(bo, target_bo);
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}
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int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
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drm_public int
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drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
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{
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if (bufmgr->get_pipe_from_crtc_id)
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return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id);
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@ -298,9 +318,8 @@ err:
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return size;
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}
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int drm_intel_get_aperture_sizes(int fd,
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size_t *mappable,
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size_t *total)
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drm_public int
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drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total)
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{
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struct drm_i915_gem_get_aperture aperture;
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@ -49,6 +49,7 @@
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#include "drm.h"
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#include "i915_drm.h"
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#include "mm.h"
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#include "libdrm.h"
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#include "libdrm_lists.h"
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/* Support gcc's __FUNCTION__ for people using other compilers */
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@ -248,7 +249,7 @@ FENCE_LTE(unsigned a, unsigned b)
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return 0;
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}
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void
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drm_public void
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drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
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unsigned int (*emit) (void *priv),
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void (*wait) (unsigned int fence,
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@ -771,7 +772,7 @@ drm_intel_fake_bo_wait_rendering(drm_intel_bo *bo)
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* -- just evict everything
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* -- and wait for idle
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*/
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void
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drm_public void
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drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr)
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{
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drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
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@ -867,7 +868,7 @@ drm_intel_fake_bo_alloc_tiled(drm_intel_bufmgr * bufmgr,
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4096);
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}
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drm_intel_bo *
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drm_public drm_intel_bo *
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drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
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const char *name,
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unsigned long offset,
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@ -962,7 +963,7 @@ drm_intel_fake_bo_unreference(drm_intel_bo *bo)
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* Set the buffer as not requiring backing store, and instead get the callback
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* invoked whenever it would be set dirty.
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*/
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void
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drm_public void
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drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
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void (*invalidate_cb) (drm_intel_bo *bo,
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void *ptr),
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@ -1416,7 +1417,7 @@ drm_intel_bo_fake_post_submit(drm_intel_bo *bo)
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bo_fake->write_domain = 0;
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}
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void
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drm_public void
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drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
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int (*exec) (drm_intel_bo *bo,
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unsigned int used,
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@ -1539,7 +1540,8 @@ drm_intel_fake_check_aperture_space(drm_intel_bo ** bo_array, int count)
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* Used by the X Server on LeaveVT, when the card memory is no longer our
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* own.
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*/
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void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr)
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drm_public void
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drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr)
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{
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drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
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struct block *block, *tmp;
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@ -1573,7 +1575,8 @@ void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr)
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pthread_mutex_unlock(&bufmgr_fake->lock);
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}
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void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
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drm_public void
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drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
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volatile unsigned int
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*last_dispatch)
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{
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@ -1582,12 +1585,10 @@ void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
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bufmgr_fake->last_dispatch = (volatile int *)last_dispatch;
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}
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drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
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unsigned long low_offset,
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void *low_virtual,
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unsigned long size,
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volatile unsigned int
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*last_dispatch)
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drm_public drm_intel_bufmgr *
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drm_intel_bufmgr_fake_init(int fd, unsigned long low_offset,
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void *low_virtual, unsigned long size,
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volatile unsigned int *last_dispatch)
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{
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drm_intel_bufmgr_fake *bufmgr_fake;
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@ -57,6 +57,7 @@
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#ifndef ETIME
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#define ETIME ETIMEDOUT
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#endif
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#include "libdrm.h"
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#include "libdrm_lists.h"
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#include "intel_bufmgr.h"
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#include "intel_bufmgr_priv.h"
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@ -853,7 +854,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
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* This can be used when one application needs to pass a buffer object
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* to another.
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*/
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drm_intel_bo *
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drm_public drm_intel_bo *
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drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
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const char *name,
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unsigned int handle)
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@ -1294,7 +1295,8 @@ map_gtt(drm_intel_bo *bo)
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return 0;
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}
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int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
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drm_public int
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drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
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{
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drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
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drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
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@ -1352,7 +1354,8 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
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* undefined).
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*/
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int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
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drm_public int
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drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
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{
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drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
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#ifdef HAVE_VALGRIND
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@ -1435,7 +1438,8 @@ static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
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return ret;
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}
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int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
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drm_public int
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drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
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{
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return drm_intel_gem_bo_unmap(bo);
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}
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|
|
@ -1550,7 +1554,8 @@ drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
|
|||
* handle. Userspace must make sure this race does not occur if such precision
|
||||
* is important.
|
||||
*/
|
||||
int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
|
||||
drm_public int
|
||||
drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
|
||||
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
|
||||
|
|
@ -1585,7 +1590,7 @@ int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
|
|||
* In combination with drm_intel_gem_bo_pin() and manual fence management, we
|
||||
* can do tiled pixmaps this way.
|
||||
*/
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
|
||||
|
|
@ -1745,7 +1750,7 @@ drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
|
|||
read_domains, write_domain, true);
|
||||
}
|
||||
|
||||
int
|
||||
drm_public int
|
||||
drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
|
||||
{
|
||||
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
|
||||
|
|
@ -1766,7 +1771,7 @@ drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
|
|||
* Any further drm_intel_bufmgr_check_aperture_space() queries
|
||||
* involving this buffer in the tree are undefined after this call.
|
||||
*/
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
|
||||
{
|
||||
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
|
||||
|
|
@ -2095,7 +2100,7 @@ aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
|
|||
bufmgr_gem->aub_offset += 4096;
|
||||
}
|
||||
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
|
||||
int x1, int y1, int width, int height,
|
||||
enum aub_dump_bmp_format format,
|
||||
|
|
@ -2366,7 +2371,7 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
|
|||
flags);
|
||||
}
|
||||
|
||||
int
|
||||
drm_public int
|
||||
drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
|
||||
int used, unsigned int flags)
|
||||
{
|
||||
|
|
@ -2485,7 +2490,7 @@ drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
|
|||
return 0;
|
||||
}
|
||||
|
||||
drm_intel_bo *
|
||||
drm_public drm_intel_bo *
|
||||
drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
|
||||
|
|
@ -2566,7 +2571,7 @@ drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int s
|
|||
return &bo_gem->bo;
|
||||
}
|
||||
|
||||
int
|
||||
drm_public int
|
||||
drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
|
||||
|
|
@ -2619,7 +2624,7 @@ drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
|
|||
* size is only bounded by how many buffers of that size we've managed to have
|
||||
* in flight at once.
|
||||
*/
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
|
||||
|
|
@ -2634,7 +2639,7 @@ drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
|
|||
* allocation. If this option is not enabled, all relocs will have fence
|
||||
* register allocated.
|
||||
*/
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
|
||||
|
|
@ -2906,7 +2911,7 @@ init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
|
|||
}
|
||||
}
|
||||
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
|
||||
|
|
@ -2948,7 +2953,7 @@ get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
|
|||
return devid;
|
||||
}
|
||||
|
||||
int
|
||||
drm_public int
|
||||
drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
|
||||
|
|
@ -2962,7 +2967,7 @@ drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
|
|||
* This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
|
||||
* for it to have any effect.
|
||||
*/
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
|
||||
const char *filename)
|
||||
{
|
||||
|
|
@ -2981,7 +2986,7 @@ drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
|
|||
* You can set up a GTT and upload your objects into the referenced
|
||||
* space, then send off batchbuffers and get BMPs out the other end.
|
||||
*/
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
|
||||
|
|
@ -3037,7 +3042,7 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
|
|||
}
|
||||
}
|
||||
|
||||
drm_intel_context *
|
||||
drm_public drm_intel_context *
|
||||
drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
|
||||
|
|
@ -3064,7 +3069,7 @@ drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
|
|||
return context;
|
||||
}
|
||||
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_gem_context_destroy(drm_intel_context *ctx)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem;
|
||||
|
|
@ -3087,7 +3092,7 @@ drm_intel_gem_context_destroy(drm_intel_context *ctx)
|
|||
free(ctx);
|
||||
}
|
||||
|
||||
int
|
||||
drm_public int
|
||||
drm_intel_get_reset_stats(drm_intel_context *ctx,
|
||||
uint32_t *reset_count,
|
||||
uint32_t *active,
|
||||
|
|
@ -3121,7 +3126,7 @@ drm_intel_get_reset_stats(drm_intel_context *ctx,
|
|||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
drm_public int
|
||||
drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
|
||||
uint32_t offset,
|
||||
uint64_t *result)
|
||||
|
|
@ -3161,7 +3166,7 @@ drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
|
|||
* default state (no annotations), call this function with a \c count
|
||||
* of zero.
|
||||
*/
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
|
||||
drm_intel_aub_annotation *annotations,
|
||||
unsigned count)
|
||||
|
|
@ -3187,7 +3192,7 @@ drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
|
|||
*
|
||||
* \param fd File descriptor of the opened DRM device.
|
||||
*/
|
||||
drm_intel_bufmgr *
|
||||
drm_public drm_intel_bufmgr *
|
||||
drm_intel_bufmgr_gem_init(int fd, int batch_size)
|
||||
{
|
||||
drm_intel_bufmgr_gem *bufmgr_gem;
|
||||
|
|
|
|||
|
|
@ -21,6 +21,10 @@
|
|||
* IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
|
@ -29,6 +33,7 @@
|
|||
#include <stdarg.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "libdrm.h"
|
||||
#include "xf86drm.h"
|
||||
#include "intel_chipset.h"
|
||||
#include "intel_bufmgr.h"
|
||||
|
|
@ -3812,7 +3817,7 @@ decode_3d_i830(struct drm_intel_decode *ctx)
|
|||
return 1;
|
||||
}
|
||||
|
||||
struct drm_intel_decode *
|
||||
drm_public struct drm_intel_decode *
|
||||
drm_intel_decode_context_alloc(uint32_t devid)
|
||||
{
|
||||
struct drm_intel_decode *ctx;
|
||||
|
|
@ -3844,20 +3849,20 @@ drm_intel_decode_context_alloc(uint32_t devid)
|
|||
return ctx;
|
||||
}
|
||||
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_decode_context_free(struct drm_intel_decode *ctx)
|
||||
{
|
||||
free(ctx);
|
||||
}
|
||||
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
|
||||
int dump_past_end)
|
||||
{
|
||||
ctx->dump_past_end = !!dump_past_end;
|
||||
}
|
||||
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
|
||||
void *data, uint32_t hw_offset, int count)
|
||||
{
|
||||
|
|
@ -3866,7 +3871,7 @@ drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
|
|||
ctx->base_count = count;
|
||||
}
|
||||
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
|
||||
uint32_t head, uint32_t tail)
|
||||
{
|
||||
|
|
@ -3874,7 +3879,7 @@ drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
|
|||
ctx->tail = tail;
|
||||
}
|
||||
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_decode_set_output_file(struct drm_intel_decode *ctx,
|
||||
FILE *out)
|
||||
{
|
||||
|
|
@ -3888,7 +3893,7 @@ drm_intel_decode_set_output_file(struct drm_intel_decode *ctx,
|
|||
* \param count number of DWORDs to decode in the batch buffer
|
||||
* \param hw_offset hardware address for the buffer
|
||||
*/
|
||||
void
|
||||
drm_public void
|
||||
drm_intel_decode(struct drm_intel_decode *ctx)
|
||||
{
|
||||
int ret;
|
||||
|
|
|
|||
Loading…
Reference in New Issue