tests/amdgpu: add bo eviction test
for(( i=1; i < 100; i++))
do
echo "Hello, Welcome $i times "
sudo ./amdgpu_test -s 1 -t 5
done
with above stricpt, run in two terminals, will reproduce Felix's swap leeking issue.
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
main
Chunming Zhou
parent
41b94a3fb6
commit
09642c073e
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@ -251,6 +251,29 @@ static inline int gpu_mem_free(amdgpu_bo_handle bo,
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return 0;
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}
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static inline int
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amdgpu_bo_alloc_wrap(amdgpu_device_handle dev, unsigned size,
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unsigned alignment, unsigned heap, uint64_t flags,
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amdgpu_bo_handle *bo)
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{
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struct amdgpu_bo_alloc_request request = {};
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amdgpu_bo_handle buf_handle;
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int r;
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request.alloc_size = size;
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request.phys_alignment = alignment;
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request.preferred_heap = heap;
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request.flags = flags;
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r = amdgpu_bo_alloc(dev, &request, &buf_handle);
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if (r)
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return r;
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*bo = buf_handle;
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return 0;
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}
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static inline int
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amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
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unsigned alignment, unsigned heap, uint64_t flags,
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@ -51,14 +51,22 @@ static void amdgpu_command_submission_sdma(void);
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static void amdgpu_userptr_test(void);
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static void amdgpu_semaphore_test(void);
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static void amdgpu_sync_dependency_test(void);
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static void amdgpu_bo_eviction_test(void);
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static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
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static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
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static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type);
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static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
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unsigned ip_type,
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int instance, int pm4_dw, uint32_t *pm4_src,
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int res_cnt, amdgpu_bo_handle *resources,
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struct amdgpu_cs_ib_info *ib_info,
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struct amdgpu_cs_request *ibs_request);
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CU_TestInfo basic_tests[] = {
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{ "Query Info Test", amdgpu_query_info_test },
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{ "Userptr Test", amdgpu_userptr_test },
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{ "bo eviction Test", amdgpu_bo_eviction_test },
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{ "Command submission Test (GFX)", amdgpu_command_submission_gfx },
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{ "Command submission Test (Compute)", amdgpu_command_submission_compute },
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{ "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence },
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@ -516,6 +524,156 @@ static void amdgpu_command_submission_gfx_cp_copy_data(void)
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amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_GFX);
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}
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static void amdgpu_bo_eviction_test(void)
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{
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const int sdma_write_length = 1024;
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const int pm4_dw = 256;
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amdgpu_context_handle context_handle;
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amdgpu_bo_handle bo1, bo2, vram_max[2], gtt_max[2];
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amdgpu_bo_handle *resources;
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uint32_t *pm4;
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struct amdgpu_cs_ib_info *ib_info;
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struct amdgpu_cs_request *ibs_request;
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uint64_t bo1_mc, bo2_mc;
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volatile unsigned char *bo1_cpu, *bo2_cpu;
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int i, j, r, loop1, loop2;
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uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
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amdgpu_va_handle bo1_va_handle, bo2_va_handle;
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struct amdgpu_heap_info vram_info, gtt_info;
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pm4 = calloc(pm4_dw, sizeof(*pm4));
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CU_ASSERT_NOT_EQUAL(pm4, NULL);
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ib_info = calloc(1, sizeof(*ib_info));
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CU_ASSERT_NOT_EQUAL(ib_info, NULL);
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ibs_request = calloc(1, sizeof(*ibs_request));
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CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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CU_ASSERT_EQUAL(r, 0);
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/* prepare resource */
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resources = calloc(4, sizeof(amdgpu_bo_handle));
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CU_ASSERT_NOT_EQUAL(resources, NULL);
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r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM,
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0, &vram_info);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[0]);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[1]);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT,
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0, >t_info);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[0]);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[1]);
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CU_ASSERT_EQUAL(r, 0);
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loop1 = loop2 = 0;
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/* run 9 circle to test all mapping combination */
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while(loop1 < 2) {
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while(loop2 < 2) {
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/* allocate UC bo1for sDMA use */
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r = amdgpu_bo_alloc_and_map(device_handle,
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sdma_write_length, 4096,
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AMDGPU_GEM_DOMAIN_GTT,
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gtt_flags[loop1], &bo1,
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(void**)&bo1_cpu, &bo1_mc,
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&bo1_va_handle);
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CU_ASSERT_EQUAL(r, 0);
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/* set bo1 */
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memset((void*)bo1_cpu, 0xaa, sdma_write_length);
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/* allocate UC bo2 for sDMA use */
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r = amdgpu_bo_alloc_and_map(device_handle,
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sdma_write_length, 4096,
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AMDGPU_GEM_DOMAIN_GTT,
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gtt_flags[loop2], &bo2,
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(void**)&bo2_cpu, &bo2_mc,
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&bo2_va_handle);
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CU_ASSERT_EQUAL(r, 0);
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/* clear bo2 */
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memset((void*)bo2_cpu, 0, sdma_write_length);
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resources[0] = bo1;
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resources[1] = bo2;
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resources[2] = vram_max[loop2];
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resources[3] = gtt_max[loop2];
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/* fulfill PM4: test DMA copy linear */
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i = j = 0;
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if (family_id == AMDGPU_FAMILY_SI) {
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pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0,
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sdma_write_length);
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pm4[i++] = 0xffffffff & bo2_mc;
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pm4[i++] = 0xffffffff & bo1_mc;
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pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
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pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
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} else {
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pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
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if (family_id >= AMDGPU_FAMILY_AI)
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pm4[i++] = sdma_write_length - 1;
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else
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pm4[i++] = sdma_write_length;
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pm4[i++] = 0;
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pm4[i++] = 0xffffffff & bo1_mc;
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pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
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pm4[i++] = 0xffffffff & bo2_mc;
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pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
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}
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amdgpu_test_exec_cs_helper(context_handle,
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AMDGPU_HW_IP_DMA, 0,
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i, pm4,
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4, resources,
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ib_info, ibs_request);
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/* verify if SDMA test result meets with expected */
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i = 0;
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while(i < sdma_write_length) {
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CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa);
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}
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r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc,
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sdma_write_length);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc,
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sdma_write_length);
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CU_ASSERT_EQUAL(r, 0);
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loop2++;
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}
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loop2 = 0;
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loop1++;
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}
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amdgpu_bo_free(vram_max[0]);
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amdgpu_bo_free(vram_max[1]);
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amdgpu_bo_free(gtt_max[0]);
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amdgpu_bo_free(gtt_max[1]);
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/* clean resources */
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free(resources);
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free(ibs_request);
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free(ib_info);
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free(pm4);
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/* end of test */
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r = amdgpu_cs_ctx_free(context_handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void amdgpu_command_submission_gfx(void)
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{
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/* write data using the CP */
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