don't draw if window is unmapped, other updates (Jeff Hartmann)
Brian Paul
parent
569da5a42e
commit
0dc99dc4b9
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@ -24,8 +24,8 @@
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors: Jeff Hartmann <jhartmann@valinux.com>
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* Keith Whitwell <keithw@valinux.com>
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* Authors: Jeff Hartmann <jhartmann@precisioninsight.com>
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* Keith Whitwell <keithw@precisioninsight.com>
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*
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*/
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@ -46,7 +46,7 @@ static void mgaEmitClipRect( drm_mga_private_t *dev_priv,
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PRIMGETPTR(dev_priv);
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/* Force reset of dwgctl (eliminates clip disable) */
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#if 1
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#if 0
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DWGSYNC, 0);
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PRIMOUTREG(MGAREG_DWGSYNC, 0);
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@ -147,7 +147,7 @@ static void mgaG400EmitTex0( drm_mga_private_t *dev_priv )
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/* This takes a max of 30 dwords */
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PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] );
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PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000);
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PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
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PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
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PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);
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@ -195,7 +195,8 @@ static void mgaG400EmitTex1( drm_mga_private_t *dev_priv )
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/* This takes 25 dwords */
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PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | TMC_map1_enable );
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PRIMOUTREG(MGAREG_TEXCTL2,
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regs[MGA_TEXREG_CTL2] | TMC_map1_enable | 0x00008000);
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PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
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PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
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PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);
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@ -218,40 +219,12 @@ static void mgaG400EmitTex1( drm_mga_private_t *dev_priv )
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PRIMOUTREG(0x2d00 + 60 * 4, regs[MGA_TEXREG_HEIGHT] | 0x40);
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PRIMOUTREG(MGAREG_TEXTRANS, 0xffff);
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PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff);
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PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] );
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PRIMADVANCE( dev_priv );
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}
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/* Required when switching from multitexturing to single texturing.
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*/
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static void mgaG400EmitTexFlush( drm_mga_private_t *dev_priv )
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{
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PRIMLOCALS;
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DRM_DEBUG("%s\n", __FUNCTION__);
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PRIMGETPTR( dev_priv );
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/* This takes 15 dwords */
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PRIMOUTREG( MGAREG_YDST, 0 );
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PRIMOUTREG( MGAREG_FXLEFT, 0 );
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PRIMOUTREG( MGAREG_FXRIGHT, 1 );
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PRIMOUTREG( MGAREG_DWGCTL, MGA_FLUSH_CMD );
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PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 1 );
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PRIMOUTREG( MGAREG_DMAPAD, 0 );
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PRIMOUTREG( MGAREG_DWGSYNC, 0x7000 );
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PRIMOUTREG( MGAREG_DMAPAD, 0 );
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PRIMOUTREG( MGAREG_TEXCTL2, 0 );
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PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 0 );
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PRIMOUTREG( MGAREG_TEXCTL2, 0x80 );
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PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 0 );
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PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000);
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PRIMADVANCE(dev_priv);
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}
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#define EMIT_PIPE 50
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static void mgaG400EmitPipe(drm_mga_private_t * dev_priv)
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{
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drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
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@ -262,25 +235,48 @@ static void mgaG400EmitPipe( drm_mga_private_t *dev_priv )
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PRIMGETPTR(dev_priv);
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/* This takes 30 dwords */
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/* This takes 50 dwords */
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/* Establish vertex size.
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*/
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if (pipe & MGA_T2) {
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PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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if (pipe & MGA_T2) {
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PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001e09);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
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PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
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PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
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PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x1e000000);
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} else {
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PRIMOUTREG( MGAREG_WIADDR2, WIA_wmode_suspend );
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if (dev_priv->WarpPipe & MGA_T2) {
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/* Flush the WARP pipe */
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PRIMOUTREG(MGAREG_YDST, 0);
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PRIMOUTREG(MGAREG_FXLEFT, 0);
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PRIMOUTREG(MGAREG_FXRIGHT, 1);
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PRIMOUTREG(MGAREG_DWGCTL, MGA_FLUSH_CMD);
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PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 1);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DWGSYNC, 0x7000);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_TEXCTL2, 0 | 0x00008000);
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PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0);
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PRIMOUTREG(MGAREG_TEXCTL2, 0x80 | 0x00008000);
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PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0);
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}
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PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001807);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
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PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
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@ -307,8 +303,9 @@ static void mgaG400EmitPipe( drm_mga_private_t *dev_priv )
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PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
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PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
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PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
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PRIMOUTREG( MGAREG_WIADDR2, (u32)(dev_priv->WarpIndex[pipe].phys_addr |
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WIA_wmode_start | WIA_wagp_agp) );
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PRIMOUTREG(MGAREG_WIADDR2,
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(u32) (dev_priv->WarpIndex[pipe].
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phys_addr | WIA_wmode_start | WIA_wagp_agp));
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PRIMADVANCE(dev_priv);
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}
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@ -337,8 +334,9 @@ static void mgaG200EmitPipe( drm_mga_private_t *dev_priv )
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PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
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PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
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PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
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PRIMOUTREG( MGAREG_WIADDR, (u32)(dev_priv->WarpIndex[pipe].phys_addr |
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WIA_wmode_start | WIA_wagp_agp) );
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PRIMOUTREG(MGAREG_WIADDR,
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(u32) (dev_priv->WarpIndex[pipe].
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phys_addr | WIA_wmode_start | WIA_wagp_agp));
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PRIMADVANCE(dev_priv);
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}
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@ -353,9 +351,6 @@ static void mgaEmitState( drm_mga_private_t *dev_priv )
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int multitex = sarea_priv->WarpPipe & MGA_T2;
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if (sarea_priv->WarpPipe != dev_priv->WarpPipe) {
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if ((dev_priv->WarpPipe & MGA_T2) && !multitex) {
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mgaG400EmitTexFlush( dev_priv );
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}
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mgaG400EmitPipe(dev_priv);
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dev_priv->WarpPipe = sarea_priv->WarpPipe;
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}
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@ -416,8 +411,7 @@ static int mgaVerifyContext(drm_mga_private_t *dev_priv )
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/* Disallow texture reads from PCI space.
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*/
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static int mgaVerifyTex(drm_mga_private_t *dev_priv,
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int unit)
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static int mgaVerifyTex(drm_mga_private_t * dev_priv, int unit)
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{
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drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
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@ -451,16 +445,13 @@ static int mgaVerifyState( drm_mga_private_t *dev_priv )
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if (dirty & MGA_UPLOAD_TEX0)
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rv |= mgaVerifyTex(dev_priv, 0);
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if (dev_priv->chipset == MGA_CARD_TYPE_G400)
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{
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if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
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if (dirty & MGA_UPLOAD_TEX1)
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rv |= mgaVerifyTex(dev_priv, 1);
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if (dirty & MGA_UPLOAD_PIPE)
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rv |= (sarea_priv->WarpPipe > MGA_MAX_G400_PIPES);
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}
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else
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{
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} else {
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if (dirty & MGA_UPLOAD_PIPE)
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rv |= (sarea_priv->WarpPipe > MGA_MAX_G200_PIPES);
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}
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@ -490,8 +481,7 @@ static int mgaVerifyIload( drm_mga_private_t *dev_priv,
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static void mga_dma_dispatch_tex_blit(drm_device_t * dev,
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unsigned long bus_address,
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int length,
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unsigned int destOrg )
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int length, unsigned int destOrg)
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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int use_agp = PDEA_pagpxfer_enable | 0x00000001;
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@ -527,8 +517,7 @@ static void mga_dma_dispatch_tex_blit( drm_device_t *dev,
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PRIMADVANCE(dev_priv);
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}
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static void mga_dma_dispatch_vertex(drm_device_t *dev,
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drm_buf_t *buf)
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static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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drm_mga_buf_priv_t *buf_priv = buf->dev_private;
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@ -547,22 +536,14 @@ static void mga_dma_dispatch_vertex(drm_device_t *dev,
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sarea_priv->nbox, sarea_priv->dirty);
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DRM_DEBUG("used : %d, total : %d\n", buf->used, buf->total);
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if(sarea_priv->WarpPipe & MGA_T2) {
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if ((buf->used/4) % 10)
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DRM_DEBUG("Multitex Buf is not aligned properly!!!\n");
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} else {
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if ((buf->used/4) % 8)
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DRM_DEBUG("Buf is not aligned properly!!!\n");
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}
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if (buf->used) {
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/* WARNING: if you change any of the state functions verify
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* these numbers (Overestimating this doesn't hurt).
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*/
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buf_priv->dispatched = 1;
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primary_needed = (30+15+15+30+25+
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10 +
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15 * MGA_NR_SAREA_CLIPRECTS);
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primary_needed = (50 + 15 + 15 + 30 + 25 +
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10 + 15 * MGA_NR_SAREA_CLIPRECTS);
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PRIM_OVERFLOW(dev, dev_priv, primary_needed);
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mgaEmitState(dev_priv);
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@ -593,7 +574,8 @@ static void mga_dma_dispatch_vertex(drm_device_t *dev,
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}
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if (buf_priv->discard) {
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if (buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv);
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if (buf_priv->dispatched == 1)
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AGEBUF(dev_priv, buf_priv);
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buf_priv->dispatched = 0;
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mga_freelist_put(dev, buf);
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}
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@ -604,8 +586,7 @@ static void mga_dma_dispatch_vertex(drm_device_t *dev,
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static void mga_dma_dispatch_indices(drm_device_t * dev,
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drm_buf_t * buf,
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unsigned int start,
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unsigned int end)
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unsigned int start, unsigned int end)
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{
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drm_mga_private_t *dev_priv = dev->dev_private;
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drm_mga_buf_priv_t *buf_priv = buf->dev_private;
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@ -627,9 +608,8 @@ static void mga_dma_dispatch_indices(drm_device_t *dev,
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* these numbers (Overestimating this doesn't hurt).
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*/
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buf_priv->dispatched = 1;
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primary_needed = (25+15+30+25+
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10 +
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15 * MGA_NR_SAREA_CLIPRECTS);
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primary_needed = (50 + 15 + 15 + 30 + 25 +
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10 + 15 * MGA_NR_SAREA_CLIPRECTS);
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PRIM_OVERFLOW(dev, dev_priv, primary_needed);
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mgaEmitState(dev_priv);
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@ -660,7 +640,8 @@ static void mga_dma_dispatch_indices(drm_device_t *dev,
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} while (++i < sarea_priv->nbox);
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}
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if (buf_priv->discard) {
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if (buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv);
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if (buf_priv->dispatched == 1)
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AGEBUF(dev_priv, buf_priv);
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buf_priv->dispatched = 0;
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mga_freelist_put(dev, buf);
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}
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@ -688,7 +669,8 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
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cmd = MGA_CLEAR_CMD | DC_atype_rstr;
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primary_needed = nbox * 70;
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if (primary_needed == 0) primary_needed = 70;
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if (primary_needed == 0)
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primary_needed = 70;
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PRIM_OVERFLOW(dev, dev_priv, primary_needed);
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PRIMGETPTR(dev_priv);
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@ -703,8 +685,10 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
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DRM_DEBUG("clear front\n");
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_YDSTLEN, (pbox[i].y1<<16)|height);
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PRIMOUTREG( MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1);
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PRIMOUTREG(MGAREG_YDSTLEN,
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(pbox[i].y1 << 16) | height);
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PRIMOUTREG(MGAREG_FXBNDRY,
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(pbox[i].x2 << 16) | pbox[i].x1);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_FCOL, clear_color);
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@ -716,8 +700,10 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
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DRM_DEBUG("clear back\n");
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_YDSTLEN, (pbox[i].y1<<16)|height );
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PRIMOUTREG( MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1 );
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PRIMOUTREG(MGAREG_YDSTLEN,
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(pbox[i].y1 << 16) | height);
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PRIMOUTREG(MGAREG_FXBNDRY,
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(pbox[i].x2 << 16) | pbox[i].x1);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_FCOL, clear_color);
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@ -729,8 +715,10 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
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DRM_DEBUG("clear depth\n");
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG( MGAREG_YDSTLEN, (pbox[i].y1<<16)|height );
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PRIMOUTREG( MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1 );
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PRIMOUTREG(MGAREG_YDSTLEN,
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(pbox[i].y1 << 16) | height);
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PRIMOUTREG(MGAREG_FXBNDRY,
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(pbox[i].x2 << 16) | pbox[i].x1);
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PRIMOUTREG(MGAREG_DMAPAD, 0);
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PRIMOUTREG(MGAREG_FCOL, clear_zval);
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@ -779,13 +767,14 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
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unsigned int start = pbox[i].y1 * dev_priv->stride / 2;
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DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
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pbox[i].x1, pbox[i].y1,
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pbox[i].x2, pbox[i].y2);
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pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2);
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PRIMOUTREG(MGAREG_AR0, start + pbox[i].x2 - 1);
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PRIMOUTREG(MGAREG_AR3, start + pbox[i].x1);
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PRIMOUTREG( MGAREG_FXBNDRY, pbox[i].x1|((pbox[i].x2 - 1)<<16) );
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PRIMOUTREG( MGAREG_YDSTLEN+MGAREG_MGA_EXEC, (pbox[i].y1<<16)|h );
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PRIMOUTREG(MGAREG_FXBNDRY,
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pbox[i].x1 | ((pbox[i].x2 - 1) << 16));
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PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC,
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(pbox[i].y1 << 16) | h);
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}
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/* Force reset of DWGCTL */
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@ -802,7 +791,8 @@ int mga_clear_bufs(struct inode *inode, struct file *filp,
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{
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drm_file_t *priv = filp->private_data;
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drm_device_t *dev = priv->dev;
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drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
|
||||
drm_mga_private_t *dev_priv =
|
||||
(drm_mga_private_t *) dev->dev_private;
|
||||
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mga_clear_t clear;
|
||||
|
||||
|
|
@ -822,8 +812,7 @@ int mga_clear_bufs(struct inode *inode, struct file *filp,
|
|||
*/
|
||||
dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX;
|
||||
mga_dma_dispatch_clear(dev, clear.flags,
|
||||
clear.clear_color,
|
||||
clear.clear_depth );
|
||||
clear.clear_color, clear.clear_depth);
|
||||
PRIMUPDATE(dev_priv);
|
||||
mga_flush_write_combine();
|
||||
mga_dma_schedule(dev, 1);
|
||||
|
|
@ -835,7 +824,8 @@ int mga_swap_bufs(struct inode *inode, struct file *filp,
|
|||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
|
||||
drm_mga_private_t *dev_priv =
|
||||
(drm_mga_private_t *) dev->dev_private;
|
||||
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
DRM_DEBUG("%s\n", __FUNCTION__);
|
||||
|
||||
|
|
@ -852,7 +842,8 @@ int mga_swap_bufs(struct inode *inode, struct file *filp,
|
|||
dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX;
|
||||
mga_dma_dispatch_swap(dev);
|
||||
PRIMUPDATE(dev_priv);
|
||||
set_bit(MGA_BUF_SWAP_PENDING, &dev_priv->current_prim->buffer_status);
|
||||
set_bit(MGA_BUF_SWAP_PENDING,
|
||||
&dev_priv->current_prim->buffer_status);
|
||||
mga_flush_write_combine();
|
||||
mga_dma_schedule(dev, 1);
|
||||
return 0;
|
||||
|
|
@ -864,7 +855,8 @@ int mga_iload(struct inode *inode, struct file *filp,
|
|||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
|
||||
drm_mga_private_t *dev_priv =
|
||||
(drm_mga_private_t *) dev->dev_private;
|
||||
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_buf_t *buf;
|
||||
drm_mga_buf_priv_t *buf_priv;
|
||||
|
|
@ -888,9 +880,7 @@ int mga_iload(struct inode *inode, struct file *filp,
|
|||
bus_address, iload.length, iload.destOrg);
|
||||
|
||||
if (mgaVerifyIload(dev_priv,
|
||||
bus_address,
|
||||
iload.destOrg,
|
||||
iload.length)) {
|
||||
bus_address, iload.destOrg, iload.length)) {
|
||||
mga_freelist_put(dev, buf);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -912,15 +902,16 @@ int mga_vertex(struct inode *inode, struct file *filp,
|
|||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
|
||||
drm_mga_private_t *dev_priv =
|
||||
(drm_mga_private_t *) dev->dev_private;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
drm_buf_t *buf;
|
||||
drm_mga_buf_priv_t *buf_priv;
|
||||
drm_mga_vertex_t vertex;
|
||||
DRM_DEBUG("%s\n", __FUNCTION__);
|
||||
|
||||
copy_from_user_ret(&vertex, (drm_mga_vertex_t *)arg, sizeof(vertex),
|
||||
-EFAULT);
|
||||
copy_from_user_ret(&vertex, (drm_mga_vertex_t *) arg,
|
||||
sizeof(vertex), -EFAULT);
|
||||
|
||||
if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
|
||||
DRM_ERROR("mga_vertex called without lock held\n");
|
||||
|
|
@ -937,7 +928,8 @@ int mga_vertex(struct inode *inode, struct file *filp,
|
|||
|
||||
if (!mgaVerifyState(dev_priv)) {
|
||||
if (vertex.discard) {
|
||||
if(buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv);
|
||||
if (buf_priv->dispatched == 1)
|
||||
AGEBUF(dev_priv, buf_priv);
|
||||
buf_priv->dispatched = 0;
|
||||
mga_freelist_put(dev, buf);
|
||||
}
|
||||
|
|
@ -959,15 +951,16 @@ int mga_indices(struct inode *inode, struct file *filp,
|
|||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
|
||||
drm_mga_private_t *dev_priv =
|
||||
(drm_mga_private_t *) dev->dev_private;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
drm_buf_t *buf;
|
||||
drm_mga_buf_priv_t *buf_priv;
|
||||
drm_mga_indices_t indices;
|
||||
DRM_DEBUG("%s\n", __FUNCTION__);
|
||||
|
||||
copy_from_user_ret(&indices, (drm_mga_indices_t *)arg, sizeof(indices),
|
||||
-EFAULT);
|
||||
copy_from_user_ret(&indices, (drm_mga_indices_t *) arg,
|
||||
sizeof(indices), -EFAULT);
|
||||
|
||||
if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
|
||||
DRM_ERROR("mga_indices called without lock held\n");
|
||||
|
|
@ -983,7 +976,8 @@ int mga_indices(struct inode *inode, struct file *filp,
|
|||
|
||||
if (!mgaVerifyState(dev_priv)) {
|
||||
if (indices.discard) {
|
||||
if(buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv);
|
||||
if (buf_priv->dispatched == 1)
|
||||
AGEBUF(dev_priv, buf_priv);
|
||||
buf_priv->dispatched = 0;
|
||||
mga_freelist_put(dev, buf);
|
||||
}
|
||||
|
|
@ -1008,16 +1002,13 @@ static int mga_dma_get_buffers(drm_device_t *dev, drm_dma_t *d)
|
|||
|
||||
for (i = d->granted_count; i < d->request_count; i++) {
|
||||
buf = mga_freelist_get(dev);
|
||||
if (!buf) break;
|
||||
if (!buf)
|
||||
break;
|
||||
buf->pid = current->pid;
|
||||
copy_to_user_ret(&d->request_indices[i],
|
||||
&buf->idx,
|
||||
sizeof(buf->idx),
|
||||
-EFAULT);
|
||||
&buf->idx, sizeof(buf->idx), -EFAULT);
|
||||
copy_to_user_ret(&d->request_sizes[i],
|
||||
&buf->total,
|
||||
sizeof(buf->total),
|
||||
-EFAULT);
|
||||
&buf->total, sizeof(buf->total), -EFAULT);
|
||||
++d->granted_count;
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -1045,7 +1036,8 @@ int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
/* Please don't send us buffers.
|
||||
*/
|
||||
if (d.send_count != 0) {
|
||||
DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
|
||||
DRM_ERROR
|
||||
("Process %d trying to send %d buffers via drmDMA\n",
|
||||
current->pid, d.send_count);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -1053,7 +1045,8 @@ int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
/* We'll send you buffers.
|
||||
*/
|
||||
if (d.request_count < 0 || d.request_count > dma->buf_count) {
|
||||
DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
|
||||
DRM_ERROR
|
||||
("Process %d trying to get %d buffers (of %d max)\n",
|
||||
current->pid, d.request_count, dma->buf_count);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue