Make sure that all state packets are handled in
radeon_check_and_fixup_packets() Fix state packet IDs of R200 cubic offsetsmain
Michel Daenzer
parent
7b62ed9aed
commit
0dea4de288
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@ -80,35 +80,56 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
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drm_file_t *filp_priv,
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int id,
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u32 *data ) {
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if ( id == RADEON_EMIT_PP_MISC &&
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radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_DEPTHOFFSET
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- RADEON_PP_MISC ) / 4] ) ) {
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DRM_ERROR( "Invalid depth buffer offset\n" );
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return DRM_ERR( EINVAL );
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} else if ( id == RADEON_EMIT_PP_CNTL &&
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radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_COLOROFFSET
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- RADEON_PP_CNTL ) / 4] ) ) {
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DRM_ERROR( "Invalid colour buffer offset\n" );
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return DRM_ERR( EINVAL );
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} else if ( id >= R200_EMIT_PP_TXOFFSET_0 &&
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id <= R200_EMIT_PP_TXOFFSET_5 &&
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radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[0] ) ) {
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DRM_ERROR( "Invalid R200 texture offset\n" );
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return DRM_ERR( EINVAL );
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} else if ( ( id == RADEON_EMIT_PP_TXFILTER_0 || id == RADEON_EMIT_PP_TXFILTER_1 ||
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id == RADEON_EMIT_PP_TXFILTER_2 /*|| id == RADEON_EMIT_PP_TXFILTER_3 ||
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id == RADEON_EMIT_PP_TXFILTER_4 || id == RADEON_EMIT_PP_TXFILTER_5*/ ) &&
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radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_PP_TXOFFSET_0
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- RADEON_PP_TXFILTER_0 ) / 4] ) ) {
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DRM_ERROR( "Invalid R100 texture offset\n" );
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return DRM_ERR( EINVAL );
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} else if ( id == R200_PP_CUBIC_OFFSET_F1_0 || id == R200_PP_CUBIC_OFFSET_F1_1 ||
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id == R200_PP_CUBIC_OFFSET_F1_2 || id == R200_PP_CUBIC_OFFSET_F1_3 ||
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id == R200_PP_CUBIC_OFFSET_F1_4 || id == R200_PP_CUBIC_OFFSET_F1_5 ) {
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switch ( id ) {
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case RADEON_EMIT_PP_MISC:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_DEPTHOFFSET
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- RADEON_PP_MISC ) / 4] ) ) {
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DRM_ERROR( "Invalid depth buffer offset\n" );
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return DRM_ERR( EINVAL );
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}
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break;
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case RADEON_EMIT_PP_CNTL:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_COLOROFFSET
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- RADEON_PP_CNTL ) / 4] ) ) {
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DRM_ERROR( "Invalid colour buffer offset\n" );
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return DRM_ERR( EINVAL );
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}
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break;
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case R200_EMIT_PP_TXOFFSET_0:
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case R200_EMIT_PP_TXOFFSET_1:
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case R200_EMIT_PP_TXOFFSET_2:
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case R200_EMIT_PP_TXOFFSET_3:
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case R200_EMIT_PP_TXOFFSET_4:
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case R200_EMIT_PP_TXOFFSET_5:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[0] ) ) {
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DRM_ERROR( "Invalid R200 texture offset\n" );
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return DRM_ERR( EINVAL );
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}
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break;
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case RADEON_EMIT_PP_TXFILTER_0:
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case RADEON_EMIT_PP_TXFILTER_1:
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case RADEON_EMIT_PP_TXFILTER_2:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_PP_TXOFFSET_0
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- RADEON_PP_TXFILTER_0 ) / 4] ) ) {
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DRM_ERROR( "Invalid R100 texture offset\n" );
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return DRM_ERR( EINVAL );
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}
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break;
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case R200_EMIT_PP_CUBIC_OFFSETS_0:
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case R200_EMIT_PP_CUBIC_OFFSETS_1:
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case R200_EMIT_PP_CUBIC_OFFSETS_2:
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case R200_EMIT_PP_CUBIC_OFFSETS_3:
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case R200_EMIT_PP_CUBIC_OFFSETS_4:
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case R200_EMIT_PP_CUBIC_OFFSETS_5: {
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int i;
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for ( i = 0; i < 5; i++ ) {
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if ( radeon_check_and_fixup_offset_user( dev_priv,
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@ -118,6 +139,74 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
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return DRM_ERR( EINVAL );
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}
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}
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break;
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}
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case RADEON_EMIT_RB3D_COLORPITCH:
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case RADEON_EMIT_RE_LINE_PATTERN:
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case RADEON_EMIT_SE_LINE_WIDTH:
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case RADEON_EMIT_PP_LUM_MATRIX:
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case RADEON_EMIT_PP_ROT_MATRIX_0:
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case RADEON_EMIT_RB3D_STENCILREFMASK:
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case RADEON_EMIT_SE_VPORT_XSCALE:
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case RADEON_EMIT_SE_CNTL:
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case RADEON_EMIT_SE_CNTL_STATUS:
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case RADEON_EMIT_RE_MISC:
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case RADEON_EMIT_PP_BORDER_COLOR_0:
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case RADEON_EMIT_PP_BORDER_COLOR_1:
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case RADEON_EMIT_PP_BORDER_COLOR_2:
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case RADEON_EMIT_SE_ZBIAS_FACTOR:
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case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
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case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
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case R200_EMIT_PP_TXCBLEND_0:
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case R200_EMIT_PP_TXCBLEND_1:
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case R200_EMIT_PP_TXCBLEND_2:
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case R200_EMIT_PP_TXCBLEND_3:
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case R200_EMIT_PP_TXCBLEND_4:
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case R200_EMIT_PP_TXCBLEND_5:
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case R200_EMIT_PP_TXCBLEND_6:
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case R200_EMIT_PP_TXCBLEND_7:
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case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
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case R200_EMIT_TFACTOR_0:
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case R200_EMIT_VTX_FMT_0:
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case R200_EMIT_VAP_CTL:
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case R200_EMIT_MATRIX_SELECT_0:
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case R200_EMIT_TEX_PROC_CTL_2:
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case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
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case R200_EMIT_PP_TXFILTER_0:
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case R200_EMIT_PP_TXFILTER_1:
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case R200_EMIT_PP_TXFILTER_2:
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case R200_EMIT_PP_TXFILTER_3:
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case R200_EMIT_PP_TXFILTER_4:
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case R200_EMIT_PP_TXFILTER_5:
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case R200_EMIT_VTE_CNTL:
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case R200_EMIT_OUTPUT_VTX_COMP_SEL:
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case R200_EMIT_PP_TAM_DEBUG3:
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case R200_EMIT_PP_CNTL_X:
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case R200_EMIT_RB3D_DEPTHXY_OFFSET:
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case R200_EMIT_RE_AUX_SCISSOR_CNTL:
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case R200_EMIT_RE_SCISSOR_TL_0:
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case R200_EMIT_RE_SCISSOR_TL_1:
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case R200_EMIT_RE_SCISSOR_TL_2:
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case R200_EMIT_SE_VAP_CNTL_STATUS:
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case R200_EMIT_SE_VTX_STATE_CNTL:
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case R200_EMIT_RE_POINTSIZE:
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case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
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case R200_EMIT_PP_CUBIC_FACES_0:
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case R200_EMIT_PP_CUBIC_FACES_1:
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case R200_EMIT_PP_CUBIC_FACES_2:
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case R200_EMIT_PP_CUBIC_FACES_3:
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case R200_EMIT_PP_CUBIC_FACES_4:
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case R200_EMIT_PP_CUBIC_FACES_5:
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case RADEON_EMIT_PP_TEX_SIZE_0:
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case RADEON_EMIT_PP_TEX_SIZE_1:
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case RADEON_EMIT_PP_TEX_SIZE_2:
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/* These packets don't contain memory offsets */
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break;
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default:
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DRM_ERROR( "Unknown state packet ID %d\n", id );
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return DRM_ERR( EINVAL );
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}
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return 0;
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@ -80,35 +80,56 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
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drm_file_t *filp_priv,
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int id,
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u32 *data ) {
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if ( id == RADEON_EMIT_PP_MISC &&
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radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_DEPTHOFFSET
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- RADEON_PP_MISC ) / 4] ) ) {
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DRM_ERROR( "Invalid depth buffer offset\n" );
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return DRM_ERR( EINVAL );
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} else if ( id == RADEON_EMIT_PP_CNTL &&
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radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_COLOROFFSET
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- RADEON_PP_CNTL ) / 4] ) ) {
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DRM_ERROR( "Invalid colour buffer offset\n" );
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return DRM_ERR( EINVAL );
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} else if ( id >= R200_EMIT_PP_TXOFFSET_0 &&
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id <= R200_EMIT_PP_TXOFFSET_5 &&
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radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[0] ) ) {
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DRM_ERROR( "Invalid R200 texture offset\n" );
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return DRM_ERR( EINVAL );
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} else if ( ( id == RADEON_EMIT_PP_TXFILTER_0 || id == RADEON_EMIT_PP_TXFILTER_1 ||
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id == RADEON_EMIT_PP_TXFILTER_2 /*|| id == RADEON_EMIT_PP_TXFILTER_3 ||
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id == RADEON_EMIT_PP_TXFILTER_4 || id == RADEON_EMIT_PP_TXFILTER_5*/ ) &&
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radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_PP_TXOFFSET_0
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- RADEON_PP_TXFILTER_0 ) / 4] ) ) {
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DRM_ERROR( "Invalid R100 texture offset\n" );
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return DRM_ERR( EINVAL );
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} else if ( id == R200_PP_CUBIC_OFFSET_F1_0 || id == R200_PP_CUBIC_OFFSET_F1_1 ||
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id == R200_PP_CUBIC_OFFSET_F1_2 || id == R200_PP_CUBIC_OFFSET_F1_3 ||
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id == R200_PP_CUBIC_OFFSET_F1_4 || id == R200_PP_CUBIC_OFFSET_F1_5 ) {
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switch ( id ) {
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case RADEON_EMIT_PP_MISC:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_DEPTHOFFSET
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- RADEON_PP_MISC ) / 4] ) ) {
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DRM_ERROR( "Invalid depth buffer offset\n" );
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return DRM_ERR( EINVAL );
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}
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break;
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case RADEON_EMIT_PP_CNTL:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_RB3D_COLOROFFSET
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- RADEON_PP_CNTL ) / 4] ) ) {
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DRM_ERROR( "Invalid colour buffer offset\n" );
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return DRM_ERR( EINVAL );
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}
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break;
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case R200_EMIT_PP_TXOFFSET_0:
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case R200_EMIT_PP_TXOFFSET_1:
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case R200_EMIT_PP_TXOFFSET_2:
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case R200_EMIT_PP_TXOFFSET_3:
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case R200_EMIT_PP_TXOFFSET_4:
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case R200_EMIT_PP_TXOFFSET_5:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[0] ) ) {
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DRM_ERROR( "Invalid R200 texture offset\n" );
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return DRM_ERR( EINVAL );
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}
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break;
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case RADEON_EMIT_PP_TXFILTER_0:
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case RADEON_EMIT_PP_TXFILTER_1:
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case RADEON_EMIT_PP_TXFILTER_2:
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if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
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&data[( RADEON_PP_TXOFFSET_0
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- RADEON_PP_TXFILTER_0 ) / 4] ) ) {
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DRM_ERROR( "Invalid R100 texture offset\n" );
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return DRM_ERR( EINVAL );
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}
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break;
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case R200_EMIT_PP_CUBIC_OFFSETS_0:
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case R200_EMIT_PP_CUBIC_OFFSETS_1:
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case R200_EMIT_PP_CUBIC_OFFSETS_2:
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case R200_EMIT_PP_CUBIC_OFFSETS_3:
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case R200_EMIT_PP_CUBIC_OFFSETS_4:
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case R200_EMIT_PP_CUBIC_OFFSETS_5: {
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int i;
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for ( i = 0; i < 5; i++ ) {
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if ( radeon_check_and_fixup_offset_user( dev_priv,
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@ -118,6 +139,74 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
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return DRM_ERR( EINVAL );
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}
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}
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break;
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}
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case RADEON_EMIT_RB3D_COLORPITCH:
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case RADEON_EMIT_RE_LINE_PATTERN:
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case RADEON_EMIT_SE_LINE_WIDTH:
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case RADEON_EMIT_PP_LUM_MATRIX:
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case RADEON_EMIT_PP_ROT_MATRIX_0:
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case RADEON_EMIT_RB3D_STENCILREFMASK:
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case RADEON_EMIT_SE_VPORT_XSCALE:
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case RADEON_EMIT_SE_CNTL:
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case RADEON_EMIT_SE_CNTL_STATUS:
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case RADEON_EMIT_RE_MISC:
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case RADEON_EMIT_PP_BORDER_COLOR_0:
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case RADEON_EMIT_PP_BORDER_COLOR_1:
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case RADEON_EMIT_PP_BORDER_COLOR_2:
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case RADEON_EMIT_SE_ZBIAS_FACTOR:
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case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
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case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
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case R200_EMIT_PP_TXCBLEND_0:
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case R200_EMIT_PP_TXCBLEND_1:
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case R200_EMIT_PP_TXCBLEND_2:
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case R200_EMIT_PP_TXCBLEND_3:
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case R200_EMIT_PP_TXCBLEND_4:
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case R200_EMIT_PP_TXCBLEND_5:
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case R200_EMIT_PP_TXCBLEND_6:
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case R200_EMIT_PP_TXCBLEND_7:
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case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
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case R200_EMIT_TFACTOR_0:
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case R200_EMIT_VTX_FMT_0:
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case R200_EMIT_VAP_CTL:
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case R200_EMIT_MATRIX_SELECT_0:
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case R200_EMIT_TEX_PROC_CTL_2:
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case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
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case R200_EMIT_PP_TXFILTER_0:
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case R200_EMIT_PP_TXFILTER_1:
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case R200_EMIT_PP_TXFILTER_2:
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case R200_EMIT_PP_TXFILTER_3:
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case R200_EMIT_PP_TXFILTER_4:
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case R200_EMIT_PP_TXFILTER_5:
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case R200_EMIT_VTE_CNTL:
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case R200_EMIT_OUTPUT_VTX_COMP_SEL:
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case R200_EMIT_PP_TAM_DEBUG3:
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case R200_EMIT_PP_CNTL_X:
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case R200_EMIT_RB3D_DEPTHXY_OFFSET:
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case R200_EMIT_RE_AUX_SCISSOR_CNTL:
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case R200_EMIT_RE_SCISSOR_TL_0:
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case R200_EMIT_RE_SCISSOR_TL_1:
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case R200_EMIT_RE_SCISSOR_TL_2:
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case R200_EMIT_SE_VAP_CNTL_STATUS:
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case R200_EMIT_SE_VTX_STATE_CNTL:
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case R200_EMIT_RE_POINTSIZE:
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case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
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case R200_EMIT_PP_CUBIC_FACES_0:
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case R200_EMIT_PP_CUBIC_FACES_1:
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case R200_EMIT_PP_CUBIC_FACES_2:
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case R200_EMIT_PP_CUBIC_FACES_3:
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case R200_EMIT_PP_CUBIC_FACES_4:
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case R200_EMIT_PP_CUBIC_FACES_5:
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case RADEON_EMIT_PP_TEX_SIZE_0:
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case RADEON_EMIT_PP_TEX_SIZE_1:
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case RADEON_EMIT_PP_TEX_SIZE_2:
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/* These packets don't contain memory offsets */
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break;
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default:
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DRM_ERROR( "Unknown state packet ID %d\n", id );
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return DRM_ERR( EINVAL );
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}
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return 0;
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