tests/amdgpu: implement VCE unit tests
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>main
Leo Liu
Alex Deucher
parent
322d02d025
commit
0f4e6702ee
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@ -23,4 +23,7 @@ amdgpu_test_SOURCES = \
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basic_tests.c \
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bo_tests.c \
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cs_tests.c \
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uvd_messages.h
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uvd_messages.h \
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vce_tests.c \
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vce_ib.h \
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frame.h
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@ -59,6 +59,8 @@ static CU_SuiteInfo suites[] = {
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suite_bo_tests_clean, bo_tests },
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{ "CS Tests", suite_cs_tests_init,
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suite_cs_tests_clean, cs_tests },
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{ "VCE Tests", suite_vce_tests_init,
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suite_vce_tests_clean, vce_tests },
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CU_SUITE_INFO_NULL,
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};
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@ -85,6 +85,21 @@ int suite_cs_tests_clean();
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*/
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extern CU_TestInfo cs_tests[];
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/**
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* Initialize vce test suite
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*/
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int suite_vce_tests_init();
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/**
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* Deinitialize vce test suite
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*/
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int suite_vce_tests_clean();
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/**
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* Tests in vce test suite
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*/
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extern CU_TestInfo vce_tests[];
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/**
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* Helper functions
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*/
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,318 @@
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _vce_ib_h_
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#define _vce_ib_h_
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static uint32_t vce_session[3] = {
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0x0000000c,
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0x00000001,
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0x400c0001,
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};
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static uint32_t vce_taskinfo[8] = {
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0x00000020,
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0x00000002,
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0xffffffff,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static uint32_t vce_create[12] = {
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0x00000030,
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0x01000001,
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0x00000000,
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0x00000042,
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0x0000002a,
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0x00000000,
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0x000000a0,
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0x00000080,
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0x000000a0,
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0x000000a0,
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0x00000010,
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0x00000000,
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};
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static uint32_t vce_rate_ctrl[28] = {
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0x00000070,
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0x04000005,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x0000001c,
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0x0000001c,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000033,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static uint32_t vce_config_ext[3] = {
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0x0000000c,
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0x04000001,
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0x00000003,
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};
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static uint32_t vce_motion_est[26] = {
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0x00000068,
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0x04000007,
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0x00000001,
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0x00000001,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000010,
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0x00000010,
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0x00000010,
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0x00000010,
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0x00000000,
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0x00000000,
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0x00000000,
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0x000000fe,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000001,
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0x00000001,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static uint32_t vce_rdo[19] = {
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0x0000004c,
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0x04000008,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static uint32_t vce_pic_ctrl[29] = {
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0x00000074,
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0x04000002,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000aa0,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000040,
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0x00000000,
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0x00000000,
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0x00000001,
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0x00000002,
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0x00000001,
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0x00000001,
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0x00000000,
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0x00000000,
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};
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static uint32_t vce_feedback[5] = {
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0x00000014,
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0x05000005,
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0x00000000,
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0xffffffff,
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0x00000001,
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};
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static uint32_t vce_context_buffer[4] = {
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0x00000010,
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0x05000001,
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0x00000000,
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0xffffffff,
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};
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static uint32_t vce_bs_buffer[5] = {
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0x00000014,
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0x05000004,
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0x00000000,
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0xffffffff,
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0x00154000,
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};
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static uint32_t vce_aux_buffer[18] = {
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0x00000048,
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0x05000002,
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0x0000f000,
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0x00016800,
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0x0001e000,
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0x00025800,
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0x0002d000,
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0x00034800,
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0x0003c000,
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0x00043800,
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0x00007800,
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0x00007800,
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0x00007800,
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0x00007800,
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0x00007800,
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0x00007800,
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0x00007800,
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0x00007800,
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};
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static uint32_t vce_encode[88] = {
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0x00000160,
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0x03000001,
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0x00000011,
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0x00000000,
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0x00154000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xffffffff,
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0x00000000,
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0xffffffff,
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0x00000080,
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0x000000a0,
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0x000000a0,
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0x00010000,
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0x00000000,
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0x00000003,
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0x00000001,
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0x00000000,
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0x00000000,
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0x00000001,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xffffffff,
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0xffffffff,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xffffffff,
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0xffffffff,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xffffffff,
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0xffffffff,
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0xffffffff,
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0xffffffff,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static uint32_t vce_destroy[2] = {
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0x00000008,
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0x02000001,
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};
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#endif /*_vce_ib_h*/
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@ -0,0 +1,461 @@
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <stdio.h>
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#include <inttypes.h>
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#include "CUnit/Basic.h"
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#include "util_math.h"
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#include "amdgpu_test.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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#include "vce_ib.h"
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#include "frame.h"
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#define IB_SIZE amdgpu_cs_ib_size_4K
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#define MAX_RESOURCES 16
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struct amdgpu_vce_bo {
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struct amdgpu_bo *handle;
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uint64_t addr;
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uint8_t *ptr;
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};
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struct amdgpu_vce_encode {
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unsigned width;
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unsigned height;
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struct amdgpu_vce_bo vbuf;
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struct amdgpu_vce_bo bs[2];
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struct amdgpu_vce_bo fb[2];
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struct amdgpu_vce_bo cpb;
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unsigned ib_len;
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bool two_instance;
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};
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static amdgpu_device_handle device_handle;
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static uint32_t major_version;
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static uint32_t minor_version;
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static uint32_t family_id;
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static amdgpu_context_handle context_handle;
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static amdgpu_ib_handle ib_handle;
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uint32_t *ib_cpu;
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struct amdgpu_vce_encode enc;
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amdgpu_bo_handle resources[MAX_RESOURCES];
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unsigned num_resources;
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static void amdgpu_cs_vce_create(void);
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static void amdgpu_cs_vce_encode(void);
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static void amdgpu_cs_vce_destroy(void);
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CU_TestInfo vce_tests[] = {
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{ "VCE create", amdgpu_cs_vce_create },
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{ "VCE encode", amdgpu_cs_vce_encode },
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{ "VCE destroy", amdgpu_cs_vce_destroy },
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CU_TEST_INFO_NULL,
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};
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int suite_vce_tests_init(void)
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{
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struct amdgpu_cs_ib_alloc_result ib_result = {0};
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int r;
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r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
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&minor_version, &device_handle);
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if (r)
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return CUE_SINIT_FAILED;
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family_id = device_handle->info.family_id;
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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if (r)
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return CUE_SINIT_FAILED;
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r = amdgpu_cs_alloc_ib(context_handle, IB_SIZE, &ib_result);
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if (r)
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return CUE_SINIT_FAILED;
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ib_handle = ib_result.handle;
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ib_cpu = ib_result.cpu;
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memset(&enc, 0, sizeof(struct amdgpu_vce_encode));
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return CUE_SUCCESS;
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}
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int suite_vce_tests_clean(void)
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{
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int r;
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r = amdgpu_cs_free_ib(ib_handle);
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if (r)
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return CUE_SCLEAN_FAILED;
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r = amdgpu_cs_ctx_free(context_handle);
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if (r)
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return CUE_SCLEAN_FAILED;
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r = amdgpu_device_deinitialize(device_handle);
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if (r)
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return CUE_SCLEAN_FAILED;
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return CUE_SUCCESS;
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}
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static int submit(unsigned ndw, unsigned ip)
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{
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struct amdgpu_cs_ib_alloc_result ib_result = {0};
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struct amdgpu_cs_request ibs_request = {0};
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struct amdgpu_cs_ib_info ib_info = {0};
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struct amdgpu_cs_query_fence fence_status = {0};
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uint32_t expired;
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int r;
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ib_info.ib_handle = ib_handle;
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ib_info.size = ndw;
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ibs_request.ip_type = ip;
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r = amdgpu_bo_list_create(device_handle, num_resources, resources,
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NULL, &ibs_request.resources);
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if (r)
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return r;
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ibs_request.number_of_ibs = 1;
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ibs_request.ibs = &ib_info;
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r = amdgpu_cs_submit(context_handle, 0,
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&ibs_request, 1, &fence_status.fence);
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if (r)
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return r;
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r = amdgpu_bo_list_destroy(ibs_request.resources);
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if (r)
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return r;
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r = amdgpu_cs_alloc_ib(context_handle, IB_SIZE, &ib_result);
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if (r)
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return r;
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ib_handle = ib_result.handle;
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ib_cpu = ib_result.cpu;
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fence_status.context = context_handle;
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fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
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fence_status.ip_type = ip;
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r = amdgpu_cs_query_fence_status(&fence_status, &expired);
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if (r)
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return r;
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return 0;
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}
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||||
static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain)
|
||||
{
|
||||
struct amdgpu_bo_alloc_request req = {0};
|
||||
struct amdgpu_bo_alloc_result res = {0};
|
||||
int r;
|
||||
|
||||
req.alloc_size = ALIGN(size, 4096);
|
||||
req.preferred_heap = domain;
|
||||
r = amdgpu_bo_alloc(device_handle, &req, &res);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
vce_bo->addr = res.virtual_mc_base_address;
|
||||
vce_bo->handle = res.buf_handle;
|
||||
r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
memset(vce_bo->ptr, 0, size);
|
||||
r = amdgpu_bo_cpu_unmap(vce_bo->handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vce_create(void)
|
||||
{
|
||||
int len, r;
|
||||
|
||||
enc.width = vce_create[6];
|
||||
enc.height = vce_create[7];
|
||||
|
||||
num_resources = 0;
|
||||
alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = enc.fb[0].handle;
|
||||
|
||||
len = 0;
|
||||
memcpy(ib_cpu, vce_session, sizeof(vce_session));
|
||||
len += sizeof(vce_session) / 4;
|
||||
memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
|
||||
len += sizeof(vce_taskinfo) / 4;
|
||||
memcpy((ib_cpu + len), vce_create, sizeof(vce_create));
|
||||
len += sizeof(vce_create) / 4;
|
||||
memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
|
||||
ib_cpu[len + 2] = enc.fb[0].addr >> 32;
|
||||
ib_cpu[len + 3] = enc.fb[0].addr;
|
||||
len += sizeof(vce_feedback) / 4;
|
||||
|
||||
r = submit(len, AMDGPU_HW_IP_VCE);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_bo_free(resources[0]);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vce_config(void)
|
||||
{
|
||||
int len = 0, r;
|
||||
|
||||
memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
|
||||
len += sizeof(vce_session) / 4;
|
||||
memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
|
||||
ib_cpu[len + 3] = 2;
|
||||
ib_cpu[len + 6] = 0xffffffff;
|
||||
len += sizeof(vce_taskinfo) / 4;
|
||||
memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl));
|
||||
len += sizeof(vce_rate_ctrl) / 4;
|
||||
memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext));
|
||||
len += sizeof(vce_config_ext) / 4;
|
||||
memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est));
|
||||
len += sizeof(vce_motion_est) / 4;
|
||||
memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo));
|
||||
len += sizeof(vce_rdo) / 4;
|
||||
memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl));
|
||||
len += sizeof(vce_pic_ctrl) / 4;
|
||||
|
||||
r = submit(len, AMDGPU_HW_IP_VCE);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc)
|
||||
{
|
||||
|
||||
uint64_t luma_offset, chroma_offset;
|
||||
int len = 0, r;
|
||||
|
||||
luma_offset = enc->vbuf.addr;
|
||||
chroma_offset = luma_offset + enc->width * enc->height;
|
||||
|
||||
memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
|
||||
len += sizeof(vce_session) / 4;
|
||||
memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
|
||||
len += sizeof(vce_taskinfo) / 4;
|
||||
memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
|
||||
ib_cpu[len + 2] = enc->bs[0].addr >> 32;
|
||||
ib_cpu[len + 3] = enc->bs[0].addr;
|
||||
len += sizeof(vce_bs_buffer) / 4;
|
||||
memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
|
||||
ib_cpu[len + 2] = enc->cpb.addr >> 32;
|
||||
ib_cpu[len + 3] = enc->cpb.addr;
|
||||
len += sizeof(vce_context_buffer) / 4;
|
||||
memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
|
||||
len += sizeof(vce_aux_buffer) / 4;
|
||||
memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
|
||||
ib_cpu[len + 2] = enc->fb[0].addr >> 32;
|
||||
ib_cpu[len + 3] = enc->fb[0].addr;
|
||||
len += sizeof(vce_feedback) / 4;
|
||||
memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
|
||||
ib_cpu[len + 9] = luma_offset >> 32;
|
||||
ib_cpu[len + 10] = luma_offset;
|
||||
ib_cpu[len + 11] = chroma_offset >> 32;
|
||||
ib_cpu[len + 12] = chroma_offset;
|
||||
ib_cpu[len + 73] = 0x7800;
|
||||
ib_cpu[len + 74] = 0x7800 + 0x5000;
|
||||
len += sizeof(vce_encode) / 4;
|
||||
enc->ib_len = len;
|
||||
if (!enc->two_instance) {
|
||||
r = submit(len, AMDGPU_HW_IP_VCE);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc)
|
||||
{
|
||||
uint64_t luma_offset, chroma_offset;
|
||||
int len, r;
|
||||
|
||||
len = (enc->two_instance) ? enc->ib_len : 0;
|
||||
luma_offset = enc->vbuf.addr;
|
||||
chroma_offset = luma_offset + enc->width * enc->height;
|
||||
|
||||
if (!enc->two_instance) {
|
||||
memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
|
||||
len += sizeof(vce_session) / 4;
|
||||
}
|
||||
memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
|
||||
len += sizeof(vce_taskinfo) / 4;
|
||||
memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
|
||||
ib_cpu[len + 2] = enc->bs[1].addr >> 32;
|
||||
ib_cpu[len + 3] = enc->bs[1].addr;
|
||||
len += sizeof(vce_bs_buffer) / 4;
|
||||
memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
|
||||
ib_cpu[len + 2] = enc->cpb.addr >> 32;
|
||||
ib_cpu[len + 3] = enc->cpb.addr;
|
||||
len += sizeof(vce_context_buffer) / 4;
|
||||
memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
|
||||
len += sizeof(vce_aux_buffer) / 4;
|
||||
memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
|
||||
ib_cpu[len + 2] = enc->fb[1].addr >> 32;
|
||||
ib_cpu[len + 3] = enc->fb[1].addr;
|
||||
len += sizeof(vce_feedback) / 4;
|
||||
memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
|
||||
ib_cpu[len + 2] = 0;
|
||||
ib_cpu[len + 9] = luma_offset >> 32;
|
||||
ib_cpu[len + 10] = luma_offset;
|
||||
ib_cpu[len + 11] = chroma_offset >> 32;
|
||||
ib_cpu[len + 12] = chroma_offset;
|
||||
ib_cpu[len + 18] = 0;
|
||||
ib_cpu[len + 19] = 0;
|
||||
ib_cpu[len + 56] = 3;
|
||||
ib_cpu[len + 57] = 0;
|
||||
ib_cpu[len + 58] = 0;
|
||||
ib_cpu[len + 59] = 0x7800;
|
||||
ib_cpu[len + 60] = 0x7800 + 0x5000;
|
||||
ib_cpu[len + 73] = 0;
|
||||
ib_cpu[len + 74] = 0x5000;
|
||||
ib_cpu[len + 81] = 1;
|
||||
ib_cpu[len + 82] = 1;
|
||||
len += sizeof(vce_encode) / 4;
|
||||
|
||||
r = submit(len, AMDGPU_HW_IP_VCE);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
static void check_result(struct amdgpu_vce_encode *enc)
|
||||
{
|
||||
uint64_t sum;
|
||||
uint32_t s[2] = {180325, 15946};
|
||||
uint32_t *ptr, size;
|
||||
int i, j, r;
|
||||
|
||||
for (i = 0; i < 2; ++i) {
|
||||
r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
ptr = (uint32_t *)enc->fb[i].ptr;
|
||||
size = ptr[4] - ptr[9];
|
||||
r = amdgpu_bo_cpu_unmap(enc->fb[i].handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
for (j = 0, sum = 0; j < size; ++j)
|
||||
sum += enc->bs[i].ptr[j];
|
||||
CU_ASSERT_EQUAL(sum, s[i]);
|
||||
r = amdgpu_bo_cpu_unmap(enc->bs[i].handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vce_encode(void)
|
||||
{
|
||||
uint32_t vbuf_size, bs_size = 0x2000, cpb_size;
|
||||
int i, r;
|
||||
|
||||
vbuf_size = enc.width * enc.height * 1.5;
|
||||
cpb_size = vbuf_size * 10;
|
||||
|
||||
num_resources = 0;
|
||||
alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = enc.fb[0].handle;
|
||||
alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = enc.fb[1].handle;
|
||||
alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = enc.bs[0].handle;
|
||||
alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = enc.bs[1].handle;
|
||||
alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
|
||||
resources[num_resources++] = enc.vbuf.handle;
|
||||
alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
|
||||
resources[num_resources++] = enc.cpb.handle;
|
||||
|
||||
r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
memcpy(enc.vbuf.ptr, frame, sizeof(frame));
|
||||
r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
amdgpu_cs_vce_config();
|
||||
|
||||
if (family_id >= AMDGPU_FAMILY_VI) {
|
||||
vce_taskinfo[3] = 3;
|
||||
amdgpu_cs_vce_encode_idr(&enc);
|
||||
amdgpu_cs_vce_encode_p(&enc);
|
||||
check_result(&enc);
|
||||
|
||||
/* two pipes */
|
||||
vce_encode[16] = 0;
|
||||
amdgpu_cs_vce_encode_idr(&enc);
|
||||
amdgpu_cs_vce_encode_p(&enc);
|
||||
check_result(&enc);
|
||||
|
||||
/* two instances */
|
||||
enc.two_instance = true;
|
||||
vce_taskinfo[2] = 0x83;
|
||||
vce_taskinfo[4] = 1;
|
||||
amdgpu_cs_vce_encode_idr(&enc);
|
||||
vce_taskinfo[2] = 0xffffffff;
|
||||
vce_taskinfo[4] = 2;
|
||||
amdgpu_cs_vce_encode_p(&enc);
|
||||
check_result(&enc);
|
||||
} else {
|
||||
vce_taskinfo[3] = 3;
|
||||
vce_encode[16] = 0;
|
||||
amdgpu_cs_vce_encode_idr(&enc);
|
||||
amdgpu_cs_vce_encode_p(&enc);
|
||||
check_result(&enc);
|
||||
}
|
||||
|
||||
for (i = 0; i < num_resources; ++i) {
|
||||
r = amdgpu_bo_free(resources[i]);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vce_destroy(void)
|
||||
{
|
||||
int len, r;
|
||||
|
||||
num_resources = 0;
|
||||
alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = enc.fb[0].handle;
|
||||
|
||||
len = 0;
|
||||
memcpy(ib_cpu, vce_session, sizeof(vce_session));
|
||||
len += sizeof(vce_session) / 4;
|
||||
memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
|
||||
ib_cpu[len + 3] = 1;
|
||||
len += sizeof(vce_taskinfo) / 4;
|
||||
memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
|
||||
ib_cpu[len + 2] = enc.fb[0].addr >> 32;
|
||||
ib_cpu[len + 3] = enc.fb[0].addr;
|
||||
len += sizeof(vce_feedback) / 4;
|
||||
memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy));
|
||||
len += sizeof(vce_destroy) / 4;
|
||||
|
||||
r = submit(len, AMDGPU_HW_IP_VCE);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_bo_free(resources[0]);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
Loading…
Reference in New Issue