Revert "nouveau: Fill in context_init for nv10-nv3x."
This reverts ac076cb9af commit.
Well it didn't do anything interesting...
main
Dave Airlie
parent
ac076cb9af
commit
125f3ff367
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@ -1,678 +0,0 @@
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/*
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* Copyright 2005-2006 Stephane Marchesin
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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/* returns the number of hw fifos */
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int nouveau_fifo_number(drm_device_t* dev)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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switch(dev_priv->card_type)
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{
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case NV_03:
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return 8;
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case NV_04:
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case NV_05:
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return 16;
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default:
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return 32;
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}
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}
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/* returns the size of fifo context */
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static int nouveau_fifo_ctx_size(drm_device_t* dev)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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if (dev_priv->card_type >= NV_40)
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return 128;
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else if (dev_priv->card_type >= NV_10)
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return 64;
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else
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return 32;
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}
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/***********************************
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* functions doing the actual work
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***********************************/
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/* voir nv_xaa.c : NVResetGraphics
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* mémoire mappée par nv_driver.c : NVMapMem
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* voir nv_driver.c : NVPreInit
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*/
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static int nouveau_fifo_instmem_configure(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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int i;
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/* Clear start of RAMIN, enough to cover RAMFC/HT/RO basically */
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for (i=0x00710000; i<0x00730000; i++)
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NV_WRITE(i, 0x00000000);
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/* FIFO hash table (RAMHT)
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* use 4k hash table at RAMIN+0x10000
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* TODO: extend the hash table
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*/
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dev_priv->ramht_offset = 0x10000;
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dev_priv->ramht_bits = 9;
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dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
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NV_WRITE(NV_PFIFO_RAMHT,
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(0x03 << 24) /* search 128 */ |
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((dev_priv->ramht_bits - 9) << 16) |
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(dev_priv->ramht_offset >> 8)
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);
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DRM_DEBUG("RAMHT offset=0x%x, size=%d\n",
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dev_priv->ramht_offset,
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dev_priv->ramht_size);
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/* FIFO runout table (RAMRO) - 512k at 0x11200 */
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dev_priv->ramro_offset = 0x11200;
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dev_priv->ramro_size = 512;
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NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
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DRM_DEBUG("RAMRO offset=0x%x, size=%d\n",
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dev_priv->ramro_offset,
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dev_priv->ramro_size);
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/* FIFO context table (RAMFC)
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* NV40 : Not sure exactly how to position RAMFC on some cards,
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* 0x30002 seems to position it at RAMIN+0x20000 on these
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* cards. RAMFC is 4kb (32 fifos, 128byte entries).
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* Others: Position RAMFC at RAMIN+0x11400
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*/
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switch(dev_priv->card_type)
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{
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case NV_50:
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case NV_40:
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dev_priv->ramfc_offset = 0x20000;
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dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
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NV_WRITE(NV40_PFIFO_RAMFC, 0x30002);
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break;
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case NV_44:
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dev_priv->ramfc_offset = 0x20000;
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dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
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NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) |
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(2 << 16));
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break;
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case NV_30:
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case NV_20:
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case NV_10:
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dev_priv->ramfc_offset = 0x11400;
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dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
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NV_WRITE(NV_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
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(1 << 16) /* 64 Bytes entry*/);
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break;
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case NV_04:
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case NV_03:
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dev_priv->ramfc_offset = 0x11400;
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dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
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NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
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break;
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}
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DRM_DEBUG("RAMFC offset=0x%x, size=%d\n",
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dev_priv->ramfc_offset,
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dev_priv->ramfc_size);
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if (nouveau_instmem_init(dev, dev_priv->ramfc_offset +
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dev_priv->ramfc_size))
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return 1;
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return 0;
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}
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int nouveau_fifo_init(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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int ret;
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NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
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ret = nouveau_fifo_instmem_configure(dev);
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if (ret) {
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DRM_ERROR("Failed to configure instance memory\n");
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return ret;
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}
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/* FIXME remove all the stuff that's done in nouveau_fifo_alloc */
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DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");
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/* All channels into PIO mode */
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NV_WRITE(NV_PFIFO_MODE, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
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/* Channel 0 active, PIO mode */
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NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000000);
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/* PUT and GET to 0 */
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NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
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/* No cmdbuf object */
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NV_WRITE(NV_PFIFO_CACH1_DMAI, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000);
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NV_WRITE(NV_PFIFO_SIZE, 0x0000FFFF);
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NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
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NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
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#ifdef __BIG_ENDIAN
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NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
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NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
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NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
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NV_PFIFO_CACH1_BIG_ENDIAN);
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#else
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NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
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NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
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NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
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#endif
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NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
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NV_WRITE(NV_PGRAPH_CTX_USER, 0x0);
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NV_WRITE(NV_PFIFO_DELAY_0, 0xff /* retrycount*/ );
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if (dev_priv->card_type >= NV_40)
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NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x00002001);
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else
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NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10110000);
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NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff);
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NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
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return 0;
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}
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static int
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nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_config *config = &dev_priv->config;
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struct mem_block *cb;
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struct nouveau_object *cb_dma = NULL;
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int cb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE);
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/* Defaults for unconfigured values */
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if (!config->cmdbuf.location)
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config->cmdbuf.location = NOUVEAU_MEM_FB;
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if (!config->cmdbuf.size || config->cmdbuf.size < cb_min_size)
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config->cmdbuf.size = cb_min_size;
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cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
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config->cmdbuf.location | NOUVEAU_MEM_MAPPED,
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(DRMFILE)-2);
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if (!cb) {
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DRM_ERROR("Couldn't allocate DMA command buffer.\n");
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return DRM_ERR(ENOMEM);
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}
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if (cb->flags & NOUVEAU_MEM_AGP) {
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cb_dma = nouveau_dma_object_create(dev,
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cb->start, cb->size,
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NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP);
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} else if (dev_priv->card_type != NV_04) {
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cb_dma = nouveau_dma_object_create(dev,
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cb->start - drm_get_resource_start(dev, 1),
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cb->size,
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NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM);
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} else {
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/* NV04 cmdbuf hack, from original ddx.. not sure of it's
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* exact reason for existing :) PCI access to cmdbuf in
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* VRAM.
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*/
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cb_dma = nouveau_dma_object_create(dev,
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cb->start, cb->size,
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NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI);
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}
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if (!cb_dma) {
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nouveau_mem_free(dev, cb);
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DRM_ERROR("Failed to alloc DMA object for command buffer\n");
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return DRM_ERR(ENOMEM);
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}
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dev_priv->fifos[channel].cmdbuf_mem = cb;
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dev_priv->fifos[channel].cmdbuf_obj = cb_dma;
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return 0;
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}
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#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV04_RAMFC_##offset, (val))
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static void nouveau_nv04_context_init(drm_device_t *dev,
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drm_nouveau_fifo_alloc_t *init)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_object *cb_obj;
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uint32_t fifoctx, ctx_size = 32;
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int i;
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cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
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fifoctx=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size;
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// clear the fifo context
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for(i=0;i<ctx_size/4;i++)
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NV_WRITE(fifoctx+4*i,0x0);
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RAMFC_WR(DMA_PUT , init->put_base);
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RAMFC_WR(DMA_GET , init->put_base);
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RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, cb_obj->instance));
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#ifdef __BIG_ENDIAN
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RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
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#else
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RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
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#endif
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}
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#undef RAMFC_WR
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#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val))
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static void nouveau_nv10_context_init(drm_device_t *dev,
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drm_nouveau_fifo_alloc_t *init)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[init->channel];
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struct nouveau_object *cb_obj;
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uint32_t fifoctx, cb_inst, ctx_size = 64;
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int i;
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cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
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cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
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fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel * ctx_size;
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for (i = 0; i < ctx_size; i += 4)
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NV_WRITE(fifoctx + i, 0);
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RAMFC_WR(DMA_PUT, init->put_base);
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RAMFC_WR(DMA_GET, init->put_base);
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RAMFC_WR(REF_CNT, NV_READ(NV_PFIFO_CACH1_REF_CNT));
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RAMFC_WR(DMA_INSTANCE, (NV_READ(NV_PFIFO_CACH1_DMA_DCOUNT) << 16) |
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NV_READ(NV_PFIFO_CACH1_DMAI));
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RAMFC_WR(DMA_STATE, NV_READ(NV_PFIFO_CACH1_DMAS));
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RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES |
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NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
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NV_PFIFO_CACH1_DMAF_MAX_REQS_8 |
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#ifdef __BIG_ENDIAN
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NV_PFIFO_CACH1_BIG_ENDIAN |
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#else
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0x00000000);
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#endif
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RAMFC_WR(ENGINE, NV_READ(NV_PFIFO_CACH1_ENG));
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RAMFC_WR(PULL1_ENGINE, NV_READ(NV_PFIFO_CACH1_PUL1));
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RAMFC_WR(ACQUIRE_VALUE, NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
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RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
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RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
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RAMFC_WR(SEMAPHORE, NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
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|
||||||
RAMFC_WR(DMA_SUBROUTINE, init->put_base);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void nouveau_nv10_context_save(drm_device_t *dev)
|
|
||||||
{
|
|
||||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
|
|
||||||
uint32_t fifoctx;
|
|
||||||
int channel;
|
|
||||||
|
|
||||||
channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
|
|
||||||
fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64;
|
|
||||||
|
|
||||||
RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP));
|
|
||||||
RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG));
|
|
||||||
RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT));
|
|
||||||
RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI));
|
|
||||||
RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS));
|
|
||||||
RAMFC_WR(DMA_FETCH , NV_READ(NV_PFIFO_CACH1_DMAF));
|
|
||||||
RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG));
|
|
||||||
RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1));
|
|
||||||
RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
|
|
||||||
RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
|
|
||||||
RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
|
|
||||||
RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
|
|
||||||
RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMASR));
|
|
||||||
}
|
|
||||||
#undef RAMFC_WR
|
|
||||||
|
|
||||||
#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val))
|
|
||||||
static void nouveau_nv40_context_init(drm_device_t *dev,
|
|
||||||
drm_nouveau_fifo_alloc_t *init)
|
|
||||||
{
|
|
||||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
|
|
||||||
struct nouveau_fifo *chan = &dev_priv->fifos[init->channel];
|
|
||||||
uint32_t fifoctx, cb_inst, grctx_inst;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
|
|
||||||
grctx_inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
|
|
||||||
fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*128;
|
|
||||||
for (i=0;i<128;i+=4)
|
|
||||||
NV_WRITE(fifoctx + i, 0);
|
|
||||||
|
|
||||||
/* Fill entries that are seen filled in dumps of nvidia driver just
|
|
||||||
* after channel's is put into DMA mode
|
|
||||||
*/
|
|
||||||
RAMFC_WR(DMA_PUT , init->put_base);
|
|
||||||
RAMFC_WR(DMA_GET , init->put_base);
|
|
||||||
RAMFC_WR(DMA_INSTANCE , cb_inst);
|
|
||||||
RAMFC_WR(DMA_FETCH , NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES |
|
|
||||||
NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
|
|
||||||
NV_PFIFO_CACH1_DMAF_MAX_REQS_8 |
|
|
||||||
#ifdef __BIG_ENDIAN
|
|
||||||
NV_PFIFO_CACH1_BIG_ENDIAN |
|
|
||||||
#endif
|
|
||||||
0x30000000 /* no idea.. */);
|
|
||||||
RAMFC_WR(DMA_SUBROUTINE, init->put_base);
|
|
||||||
RAMFC_WR(GRCTX_INSTANCE, grctx_inst);
|
|
||||||
RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void nouveau_nv40_context_save(drm_device_t *dev)
|
|
||||||
{
|
|
||||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
|
|
||||||
uint32_t fifoctx;
|
|
||||||
int channel;
|
|
||||||
|
|
||||||
channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
|
|
||||||
fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128;
|
|
||||||
|
|
||||||
RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP));
|
|
||||||
RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG));
|
|
||||||
RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT));
|
|
||||||
RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI));
|
|
||||||
RAMFC_WR(DMA_DCOUNT , NV_READ(NV_PFIFO_CACH1_DMA_DCOUNT));
|
|
||||||
RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS));
|
|
||||||
RAMFC_WR(DMA_FETCH , NV_READ(NV_PFIFO_CACH1_DMAF));
|
|
||||||
RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG));
|
|
||||||
RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1));
|
|
||||||
RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
|
|
||||||
RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
|
|
||||||
RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
|
|
||||||
RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
|
|
||||||
RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMAG));
|
|
||||||
RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE));
|
|
||||||
RAMFC_WR(DMA_TIMESLICE , NV_READ(NV_PFIFO_DMA_TIMESLICE) & 0x1FFFF);
|
|
||||||
RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4));
|
|
||||||
}
|
|
||||||
#undef RAMFC_WR
|
|
||||||
|
|
||||||
/* This function should load values from RAMFC into PFIFO, but for now
|
|
||||||
* it just clobbers PFIFO with what nouveau_fifo_alloc used to setup
|
|
||||||
* unconditionally.
|
|
||||||
*/
|
|
||||||
static void
|
|
||||||
nouveau_fifo_context_restore(drm_device_t *dev, int channel)
|
|
||||||
{
|
|
||||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
|
|
||||||
struct nouveau_fifo *chan = &dev_priv->fifos[channel];
|
|
||||||
uint32_t cb_inst;
|
|
||||||
|
|
||||||
cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
|
|
||||||
|
|
||||||
// FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF);
|
|
||||||
|
|
||||||
if (dev_priv->card_type >= NV_40)
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|channel);
|
|
||||||
else
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|channel);
|
|
||||||
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_DMAP, 0 /*RAMFC_DMA_PUT*/);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_DMAG, 0 /*RAMFC_DMA_GET*/);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_DMAI, cb_inst);
|
|
||||||
NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
|
|
||||||
|
|
||||||
NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
|
|
||||||
#ifdef __BIG_ENDIAN
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
|
|
||||||
#else
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/* allocates and initializes a fifo for user space consumption */
|
|
||||||
static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, DRMFILE filp)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
int ret;
|
|
||||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
|
|
||||||
struct nouveau_object *cb_obj;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Alright, here is the full story
|
|
||||||
* Nvidia cards have multiple hw fifo contexts (praise them for that,
|
|
||||||
* no complicated crash-prone context switches)
|
|
||||||
* We allocate a new context for each app and let it write to it directly
|
|
||||||
* (woo, full userspace command submission !)
|
|
||||||
* When there are no more contexts, you lost
|
|
||||||
*/
|
|
||||||
for(i=0;i<nouveau_fifo_number(dev);i++)
|
|
||||||
if (dev_priv->fifos[i].used==0)
|
|
||||||
break;
|
|
||||||
|
|
||||||
DRM_INFO("Allocating FIFO number %d\n", i);
|
|
||||||
/* no more fifos. you lost. */
|
|
||||||
if (i==nouveau_fifo_number(dev))
|
|
||||||
return DRM_ERR(EINVAL);
|
|
||||||
|
|
||||||
/* allocate a command buffer, and create a dma object for the gpu */
|
|
||||||
ret = nouveau_fifo_cmdbuf_alloc(dev, i);
|
|
||||||
if (ret) return ret;
|
|
||||||
cb_obj = dev_priv->fifos[i].cmdbuf_obj;
|
|
||||||
|
|
||||||
/* that fifo is used */
|
|
||||||
dev_priv->fifos[i].used=1;
|
|
||||||
dev_priv->fifos[i].filp=filp;
|
|
||||||
|
|
||||||
init->channel = i;
|
|
||||||
init->put_base = 0;
|
|
||||||
dev_priv->cur_fifo = init->channel;
|
|
||||||
dev_priv->fifos[i].pgraph_ctx_user = i << 24;
|
|
||||||
|
|
||||||
nouveau_wait_for_idle(dev);
|
|
||||||
|
|
||||||
/* disable the fifo caches */
|
|
||||||
NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_DMAPSH, NV_READ(NV_PFIFO_CACH1_DMAPSH)&(~0x1));
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
|
|
||||||
|
|
||||||
/* Construct inital RAMFC for new channel */
|
|
||||||
if (dev_priv->card_type < NV_10) {
|
|
||||||
nouveau_nv04_context_init(dev, init);
|
|
||||||
} else if (dev_priv->card_type < NV_40) {
|
|
||||||
nouveau_nv10_context_init(dev, init);
|
|
||||||
} else {
|
|
||||||
ret = nv40_graph_context_create(dev, init->channel);
|
|
||||||
if (ret) {
|
|
||||||
nouveau_fifo_free(dev, init->channel);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
nouveau_nv40_context_init(dev, init);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* enable the fifo dma operation */
|
|
||||||
NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel));
|
|
||||||
|
|
||||||
/* setup channel's default get/put values */
|
|
||||||
NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base);
|
|
||||||
NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base);
|
|
||||||
|
|
||||||
/* If this is the first channel, setup PFIFO ourselves. For any
|
|
||||||
* other case, the GPU will handle this when it switches contexts.
|
|
||||||
*/
|
|
||||||
if (dev_priv->fifo_alloc_count == 0) {
|
|
||||||
nouveau_fifo_context_restore(dev, init->channel);
|
|
||||||
if (dev_priv->card_type >= NV_40) {
|
|
||||||
struct nouveau_fifo *chan;
|
|
||||||
uint32_t inst;
|
|
||||||
|
|
||||||
chan = &dev_priv->fifos[init->channel];
|
|
||||||
inst = nouveau_chip_instance_get(dev,
|
|
||||||
chan->ramin_grctx);
|
|
||||||
|
|
||||||
/* see comments in nv40_graph_context_restore() */
|
|
||||||
NV_WRITE(0x400784, inst);
|
|
||||||
NV_WRITE(0x40032C, inst | 0x01000000);
|
|
||||||
NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
|
|
||||||
NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
|
|
||||||
|
|
||||||
/* reenable the fifo caches */
|
|
||||||
NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
|
|
||||||
|
|
||||||
/* make the fifo available to user space */
|
|
||||||
/* first, the fifo control regs */
|
|
||||||
init->ctrl = dev_priv->mmio->offset + NV03_FIFO_REGS(init->channel);
|
|
||||||
init->ctrl_size = NV03_FIFO_REGS_SIZE;
|
|
||||||
ret = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
|
|
||||||
0, &dev_priv->fifos[init->channel].regs);
|
|
||||||
if (ret != 0)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
/* pass back FIFO map info to the caller */
|
|
||||||
init->cmdbuf = dev_priv->fifos[init->channel].cmdbuf_mem->start;
|
|
||||||
init->cmdbuf_size = dev_priv->fifos[init->channel].cmdbuf_mem->size;
|
|
||||||
|
|
||||||
/* FIFO has no objects yet */
|
|
||||||
dev_priv->fifos[init->channel].objs = NULL;
|
|
||||||
dev_priv->fifo_alloc_count++;
|
|
||||||
|
|
||||||
DRM_INFO("%s: initialised FIFO %d\n", __func__, init->channel);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* stops a fifo */
|
|
||||||
void nouveau_fifo_free(drm_device_t* dev,int n)
|
|
||||||
{
|
|
||||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
|
|
||||||
int i;
|
|
||||||
int ctx_size = nouveau_fifo_ctx_size(dev);
|
|
||||||
|
|
||||||
dev_priv->fifos[n].used=0;
|
|
||||||
DRM_INFO("%s: freeing fifo %d\n", __func__, n);
|
|
||||||
|
|
||||||
/* disable the fifo caches */
|
|
||||||
NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
|
|
||||||
|
|
||||||
NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)&~(1<<n));
|
|
||||||
// FIXME XXX needs more code
|
|
||||||
|
|
||||||
/* Clean RAMFC */
|
|
||||||
for (i=0;i<ctx_size;i+=4) {
|
|
||||||
DRM_DEBUG("RAMFC +%02x: 0x%08x\n", i, NV_READ(NV_RAMIN +
|
|
||||||
dev_priv->ramfc_offset + n*ctx_size + i));
|
|
||||||
NV_WRITE(NV_RAMIN + dev_priv->ramfc_offset + n*ctx_size + i, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (dev_priv->card_type >= NV_40)
|
|
||||||
nouveau_instmem_free(dev, dev_priv->fifos[n].ramin_grctx);
|
|
||||||
|
|
||||||
/* reenable the fifo caches */
|
|
||||||
NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
|
|
||||||
|
|
||||||
/* Deallocate command buffer, and dma object */
|
|
||||||
nouveau_mem_free(dev, dev_priv->fifos[n].cmdbuf_mem);
|
|
||||||
|
|
||||||
dev_priv->fifo_alloc_count--;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* cleanups all the fifos from filp */
|
|
||||||
void nouveau_fifo_cleanup(drm_device_t* dev, DRMFILE filp)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
|
|
||||||
|
|
||||||
DRM_DEBUG("clearing FIFO enables from filp\n");
|
|
||||||
for(i=0;i<nouveau_fifo_number(dev);i++)
|
|
||||||
if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp==filp)
|
|
||||||
nouveau_fifo_free(dev,i);
|
|
||||||
|
|
||||||
/* check we still point at an active channel */
|
|
||||||
if (dev_priv->fifos[dev_priv->cur_fifo].used == 0) {
|
|
||||||
DRM_DEBUG("%s: cur_fifo is no longer owned.\n", __func__);
|
|
||||||
for (i=0;i<nouveau_fifo_number(dev);i++)
|
|
||||||
if (dev_priv->fifos[i].used) break;
|
|
||||||
if (i==nouveau_fifo_number(dev))
|
|
||||||
i=0;
|
|
||||||
DRM_DEBUG("%s: new cur_fifo is %d\n", __func__, i);
|
|
||||||
dev_priv->cur_fifo = i;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* if (dev_priv->cmdbuf_alloc)
|
|
||||||
nouveau_fifo_init(dev);*/
|
|
||||||
}
|
|
||||||
|
|
||||||
int nouveau_fifo_id_get(drm_device_t* dev, DRMFILE filp)
|
|
||||||
{
|
|
||||||
drm_nouveau_private_t *dev_priv=dev->dev_private;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for(i=0;i<nouveau_fifo_number(dev);i++)
|
|
||||||
if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp == filp)
|
|
||||||
return i;
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/***********************************
|
|
||||||
* ioctls wrapping the functions
|
|
||||||
***********************************/
|
|
||||||
|
|
||||||
static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS)
|
|
||||||
{
|
|
||||||
DRM_DEVICE;
|
|
||||||
drm_nouveau_fifo_alloc_t init;
|
|
||||||
int res;
|
|
||||||
DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, sizeof(init));
|
|
||||||
|
|
||||||
res=nouveau_fifo_alloc(dev,&init,filp);
|
|
||||||
if (!res)
|
|
||||||
DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, init, sizeof(init));
|
|
||||||
|
|
||||||
return res;
|
|
||||||
}
|
|
||||||
|
|
||||||
/***********************************
|
|
||||||
* finally, the ioctl table
|
|
||||||
***********************************/
|
|
||||||
|
|
||||||
drm_ioctl_desc_t nouveau_ioctls[] = {
|
|
||||||
[DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_ALLOC)] = {nouveau_ioctl_fifo_alloc, DRM_AUTH},
|
|
||||||
[DRM_IOCTL_NR(DRM_NOUVEAU_OBJECT_INIT)] = {nouveau_ioctl_object_init, DRM_AUTH},
|
|
||||||
[DRM_IOCTL_NR(DRM_NOUVEAU_DMA_OBJECT_INIT)] = {nouveau_ioctl_dma_object_init, DRM_AUTH},
|
|
||||||
[DRM_IOCTL_NR(DRM_NOUVEAU_MEM_ALLOC)] = {nouveau_ioctl_mem_alloc, DRM_AUTH},
|
|
||||||
[DRM_IOCTL_NR(DRM_NOUVEAU_MEM_FREE)] = {nouveau_ioctl_mem_free, DRM_AUTH},
|
|
||||||
[DRM_IOCTL_NR(DRM_NOUVEAU_GETPARAM)] = {nouveau_ioctl_getparam, DRM_AUTH},
|
|
||||||
[DRM_IOCTL_NR(DRM_NOUVEAU_SETPARAM)] = {nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
|
|
||||||
};
|
|
||||||
|
|
||||||
int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1 @@
|
||||||
|
../shared-core/nouveau_fifo.c
|
||||||
Loading…
Reference in New Issue