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amdgpu: Switch amdgpu CS tests enabling to the new way. 

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
main
Andrey Grodzovsky 2017-11-24 15:50:51 -05:00
parent 0ab36dafaf
commit 1a129004a8
3 changed files with 36 additions and 31 deletions
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2
tests/amdgpu/amdgpu_test.c
View File

@ -146,7 +146,7 @@ static Suites_Active_Status suites_active_stat[] = {
},
{
.pName = CS_TESTS_STR,
.pActive = always_active,
.pActive = suite_cs_tests_enable,
},
{
.pName = VCE_TESTS_STR,

5
tests/amdgpu/amdgpu_test.h
View File

@ -84,6 +84,11 @@ int suite_cs_tests_init();
*/
int suite_cs_tests_clean();
/**
* Decide if the suite is enabled by default or not.
*/
CU_BOOL suite_cs_tests_enable(void);
/**
* Tests in cs test suite
*/

60
tests/amdgpu/cs_tests.c
View File

@ -66,6 +66,26 @@ CU_TestInfo cs_tests[] = {
CU_TEST_INFO_NULL,
};
CU_BOOL suite_cs_tests_enable(void)
{
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
family_id = device_handle->info.family_id;
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
printf("\n\nThe ASIC NOT support UVD, suite disabled\n");
return CU_FALSE;
}
return CU_TRUE;
}
int suite_cs_tests_init(void)
{
amdgpu_bo_handle ib_result_handle;
@ -90,11 +110,6 @@ int suite_cs_tests_init(void)
chip_rev = device_handle->info.chip_rev;
chip_id = device_handle->info.chip_external_rev;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n");
return CUE_SUCCESS;
}
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
if (r)
return CUE_SINIT_FAILED;
@ -119,24 +134,18 @@ int suite_cs_tests_clean(void)
{
int r;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
} else {
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_cs_ctx_free(context_handle);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_cs_ctx_free(context_handle);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
}
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
return CUE_SUCCESS;
}
@ -203,9 +212,6 @@ static void amdgpu_cs_uvd_create(void)
void *msg;
int i, r;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI)
return;
req.alloc_size = 4*1024;
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
@ -277,9 +283,6 @@ static void amdgpu_cs_uvd_decode(void)
uint8_t *ptr;
int i, r;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI)
return;
req.alloc_size = 4*1024; /* msg */
req.alloc_size += 4*1024; /* fb */
if (family_id >= AMDGPU_FAMILY_VI)
@ -419,9 +422,6 @@ static void amdgpu_cs_uvd_destroy(void)
void *msg;
int i, r;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI)
return;
req.alloc_size = 4*1024;
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;