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intel: add support for ICL 11 

Add the PCI IDs and the basic code to enable ICL.  This is the current
PCI ID list in our documentation.

Kernel commit: d55cb4fa2cf0 ("drm/i915/icl: Add the ICL PCI IDs")

v2: Michel provided a fix to IS_9XX that was broken by rebase bot.
v3: Fix double definition of PCI IDs, update IDs according to bspec
    and keep them in the same order and rebase (Lucas)

Cc: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
main
Paulo Zanoni 2018-04-25 17:09:37 -07:00
parent bc9c789073
commit 1ac3ecde2f
3 changed files with 31 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
intel/intel_bufmgr_gem.c
View File

@ -3660,6 +3660,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->gen = 9;
else if (IS_GEN10(bufmgr_gem->pci_device))
bufmgr_gem->gen = 10;
else if (IS_GEN11(bufmgr_gem->pci_device))
bufmgr_gem->gen = 11;
else {
free(bufmgr_gem);
bufmgr_gem = NULL;

27
intel/intel_chipset.h
View File

@ -257,6 +257,16 @@
#define PCI_CHIP_CANNONLAKE_12 0x5A44
#define PCI_CHIP_CANNONLAKE_13 0x5A4C
#define PCI_CHIP_ICELAKE_11_0 0x8A50
#define PCI_CHIP_ICELAKE_11_1 0x8A51
#define PCI_CHIP_ICELAKE_11_2 0x8A5C
#define PCI_CHIP_ICELAKE_11_3 0x8A5D
#define PCI_CHIP_ICELAKE_11_4 0x8A52
#define PCI_CHIP_ICELAKE_11_5 0x8A5A
#define PCI_CHIP_ICELAKE_11_6 0x8A5B
#define PCI_CHIP_ICELAKE_11_7 0x8A71
#define PCI_CHIP_ICELAKE_11_8 0x8A70
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
(devid) == PCI_CHIP_I945_GM || \
@ -538,6 +548,20 @@
#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
#define IS_ICELAKE_11(devid) ((devid) == PCI_CHIP_ICELAKE_11_0 || \
(devid) == PCI_CHIP_ICELAKE_11_1 || \
(devid) == PCI_CHIP_ICELAKE_11_2 || \
(devid) == PCI_CHIP_ICELAKE_11_3 || \
(devid) == PCI_CHIP_ICELAKE_11_4 || \
(devid) == PCI_CHIP_ICELAKE_11_5 || \
(devid) == PCI_CHIP_ICELAKE_11_6 || \
(devid) == PCI_CHIP_ICELAKE_11_7 || \
(devid) == PCI_CHIP_ICELAKE_11_8)
#define IS_ICELAKE(devid) (IS_ICELAKE_11(devid))
#define IS_GEN11(devid) (IS_ICELAKE_11(devid))
#define IS_9XX(dev) (IS_GEN3(dev) || \
IS_GEN4(dev) || \
IS_GEN5(dev) || \
@ -545,6 +569,7 @@
IS_GEN7(dev) || \
IS_GEN8(dev) || \
IS_GEN9(dev) || \
IS_GEN10(dev))
IS_GEN10(dev) || \
IS_GEN11(dev))
#endif /* _INTEL_CHIPSET_H */

4
intel/intel_decode.c
View File

@ -3823,7 +3823,9 @@ drm_intel_decode_context_alloc(uint32_t devid)
ctx->devid = devid;
ctx->out = stdout;
if (IS_GEN10(devid))
if (IS_GEN11(devid))
ctx->gen = 11;
else if (IS_GEN10(devid))
ctx->gen = 10;
else if (IS_GEN9(devid))
ctx->gen = 9;