libdrm: headers: Sync with drm-next
Generated using make headers_install from the drm-next
tree - git://anongit.freedesktop.org/drm/drm
branch - drm-next
commit - 2dc7bad71cd310dc94d1c9907909324dd2b0618f
The changes were as follows :-
core: (drm.h, drm_fourcc.h, drm_mode.h)
- Added client capabilities for ASPECT_RATIO and WRITEBACK_CONNECTORS
- Added Arm AFBC modifiers
- Added BROADCOM's SAND and UIF modifiers
- Added Qualcomm's modifiers
- Added some picture aspect ratio and content type options
- Added some drm mode flags
- Added writeback connector id
amdgpu:
- Added GEM domain mask
- Added some GEM flags
- Added some hardware ip flags
- Added chunk id and IB fence.
- Added some query ids
i915:
-Added an IOCTL (I915_PARAM_MMAP_GTT_COHERENT)
qxl:
- Minor changes
tegra:
- Added some comments about struct drm_tegra* members
- Modified DRM_IOCTL_TEGRA_CLOSE_CHANNEL
vc4:
- Added some members for 'struct drm_vc4_submit_cl'
Changes in v2:
- Mentioned 'libdrm' in the commit header.
Changes in v3:
- Removed the changes to radeon_drm.h, sis_drm.h and via_drm.h as suggested by
Emil Velikov <emil.l.velikov@gmail.com>
Changes in v4:
- Removed the changes to vmwgfx_drm.h as it caused a build break ie
'make check' failed.
Change-Id: I018a06f65bf4a6a68400ab252b9cd05d041299b3
Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
main
Ayan Kumar Halder
Emil Velikov
parent
e08b7f2234
commit
1b18f508c8
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@ -72,12 +72,41 @@ extern "C" {
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#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
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#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
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/**
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* DOC: memory domains
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*
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* %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
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* Memory in this pool could be swapped out to disk if there is pressure.
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*
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* %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
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* GPU's virtual address space via gart. Gart memory linearizes non-contiguous
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* pages of system memory, allows GPU access system memory in a linezrized
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* fashion.
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*
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* %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
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* carved out by the BIOS.
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*
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* %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
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* across shader threads.
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*
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* %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
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* execution of all the waves on a device.
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*
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* %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
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* for appending data.
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*/
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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#define AMDGPU_GEM_DOMAIN_VRAM 0x4
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#define AMDGPU_GEM_DOMAIN_GDS 0x8
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#define AMDGPU_GEM_DOMAIN_GWS 0x10
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#define AMDGPU_GEM_DOMAIN_OA 0x20
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#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
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AMDGPU_GEM_DOMAIN_GTT | \
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AMDGPU_GEM_DOMAIN_VRAM | \
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AMDGPU_GEM_DOMAIN_GDS | \
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AMDGPU_GEM_DOMAIN_GWS | \
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AMDGPU_GEM_DOMAIN_OA)
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/* Flag that CPU access will be required for the case of VRAM domain */
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#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
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@ -95,6 +124,10 @@ extern "C" {
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#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
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/* Flag that BO sharing will be explicitly synchronized */
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#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
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/* Flag that indicates allocating MQD gart on GFX9, where the mtype
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* for the second page onward should be set to NC.
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*/
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#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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@ -473,7 +506,8 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_HW_IP_UVD_ENC 5
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#define AMDGPU_HW_IP_VCN_DEC 6
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#define AMDGPU_HW_IP_VCN_ENC 7
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#define AMDGPU_HW_IP_NUM 8
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#define AMDGPU_HW_IP_VCN_JPEG 8
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#define AMDGPU_HW_IP_NUM 9
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#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
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@ -482,6 +516,7 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
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#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
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#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
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#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
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struct drm_amdgpu_cs_chunk {
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__u32 chunk_id;
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@ -520,6 +555,10 @@ union drm_amdgpu_cs {
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/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
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#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
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/* The IB fence should do the L2 writeback but not invalidate any shader
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* caches (L2/vL1/sL1/I$). */
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#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
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struct drm_amdgpu_cs_chunk_ib {
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__u32 _pad;
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/** AMDGPU_IB_FLAG_* */
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@ -620,6 +659,12 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_FW_ASD 0x0d
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/* Subquery id: Query VCN firmware version */
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#define AMDGPU_INFO_FW_VCN 0x0e
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/* Subquery id: Query GFX RLC SRLC firmware version */
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#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
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/* Subquery id: Query GFX RLC SRLG firmware version */
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#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
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/* Subquery id: Query GFX RLC SRLS firmware version */
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#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
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/* number of bytes moved for TTM migration */
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#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
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/* the used VRAM size */
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@ -674,6 +674,22 @@ struct drm_get_cap {
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*/
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#define DRM_CLIENT_CAP_ATOMIC 3
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/**
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* DRM_CLIENT_CAP_ASPECT_RATIO
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*
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* If set to 1, the DRM core will provide aspect ratio information in modes.
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*/
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#define DRM_CLIENT_CAP_ASPECT_RATIO 4
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/**
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* DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
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*
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* If set to 1, the DRM core will expose special connectors to be used for
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* writing back to memory the scene setup in the commit. Depends on client
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* also supporting DRM_CLIENT_CAP_ATOMIC
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*/
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#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
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/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
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struct drm_set_client_cap {
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__u64 capability;
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@ -30,11 +30,50 @@
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extern "C" {
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#endif
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/**
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* DOC: overview
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*
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* In the DRM subsystem, framebuffer pixel formats are described using the
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* fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
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* fourcc code, a Format Modifier may optionally be provided, in order to
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* further describe the buffer's format - for example tiling or compression.
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*
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* Format Modifiers
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* ----------------
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*
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* Format modifiers are used in conjunction with a fourcc code, forming a
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* unique fourcc:modifier pair. This format:modifier pair must fully define the
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* format and data layout of the buffer, and should be the only way to describe
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* that particular buffer.
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*
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* Having multiple fourcc:modifier pairs which describe the same layout should
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* be avoided, as such aliases run the risk of different drivers exposing
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* different names for the same data format, forcing userspace to understand
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* that they are aliases.
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*
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* Format modifiers may change any property of the buffer, including the number
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* of planes and/or the required allocation size. Format modifiers are
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* vendor-namespaced, and as such the relationship between a fourcc code and a
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* modifier is specific to the modifer being used. For example, some modifiers
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* may preserve meaning - such as number of planes - from the fourcc code,
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* whereas others may not.
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*
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* Vendors should document their modifier usage in as much detail as
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* possible, to ensure maximum compatibility across devices, drivers and
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* applications.
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*
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* The authoritative list of format modifier codes is found in
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* `include/uapi/drm/drm_fourcc.h`
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*/
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#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
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((__u32)(c) << 16) | ((__u32)(d) << 24))
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#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
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/* Reserve 0 for the invalid format specifier */
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#define DRM_FORMAT_INVALID 0
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/* color index */
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#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
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@ -183,6 +222,7 @@ extern "C" {
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#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
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#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
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#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
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#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
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/* add more to the end as needed */
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#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
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@ -298,6 +338,19 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
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/*
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* Qualcomm Compressed Format
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*
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* Refers to a compressed variant of the base format that is compressed.
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* Implementation may be platform and base-format specific.
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*
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* Each macrotile consists of m x n (mostly 4 x 4) tiles.
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* Pixel data pitch/stride is aligned with macrotile width.
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* Pixel data height is aligned with macrotile height.
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* Entire pixel data buffer is aligned with 4k(bytes).
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*/
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#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
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/* Vivante framebuffer modifiers */
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/*
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@ -384,6 +437,23 @@ extern "C" {
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
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fourcc_mod_code(NVIDIA, 0x15)
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/*
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* Some Broadcom modifiers take parameters, for example the number of
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* vertical lines in the image. Reserve the lower 32 bits for modifier
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* type, and the next 24 bits for parameters. Top 8 bits are the
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* vendor code.
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*/
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#define __fourcc_mod_broadcom_param_shift 8
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#define __fourcc_mod_broadcom_param_bits 48
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#define fourcc_mod_broadcom_code(val, params) \
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fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
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#define fourcc_mod_broadcom_param(m) \
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((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
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((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
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#define fourcc_mod_broadcom_mod(m) \
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((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
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__fourcc_mod_broadcom_param_shift))
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/*
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* Broadcom VC4 "T" format
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*
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@ -405,6 +475,151 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
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/*
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* Broadcom SAND format
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*
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* This is the native format that the H.264 codec block uses. For VC4
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* HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
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*
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* The image can be considered to be split into columns, and the
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* columns are placed consecutively into memory. The width of those
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* columns can be either 32, 64, 128, or 256 pixels, but in practice
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* only 128 pixel columns are used.
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*
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* The pitch between the start of each column is set to optimally
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* switch between SDRAM banks. This is passed as the number of lines
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* of column width in the modifier (we can't use the stride value due
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* to various core checks that look at it , so you should set the
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* stride to width*cpp).
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*
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* Note that the column height for this format modifier is the same
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* for all of the planes, assuming that each column contains both Y
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* and UV. Some SAND-using hardware stores UV in a separate tiled
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* image from Y to reduce the column height, which is not supported
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* with these modifiers.
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*/
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#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
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fourcc_mod_broadcom_code(2, v)
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#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
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fourcc_mod_broadcom_code(3, v)
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#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
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fourcc_mod_broadcom_code(4, v)
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#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
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fourcc_mod_broadcom_code(5, v)
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#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
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DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
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#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
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DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
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#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
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DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
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#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
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DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
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/* Broadcom UIF format
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*
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* This is the common format for the current Broadcom multimedia
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* blocks, including V3D 3.x and newer, newer video codecs, and
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* displays.
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*
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* The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
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* and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
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* stored in columns, with padding between the columns to ensure that
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* moving from one column to the next doesn't hit the same SDRAM page
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* bank.
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*
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* To calculate the padding, it is assumed that each hardware block
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* and the software driving it knows the platform's SDRAM page size,
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* number of banks, and XOR address, and that it's identical between
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* all blocks using the format. This tiling modifier will use XOR as
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* necessary to reduce the padding. If a hardware block can't do XOR,
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* the assumption is that a no-XOR tiling modifier will be created.
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*/
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#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
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/*
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* Arm Framebuffer Compression (AFBC) modifiers
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*
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* AFBC is a proprietary lossless image compression protocol and format.
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* It provides fine-grained random access and minimizes the amount of data
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* transferred between IP blocks.
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*
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* AFBC has several features which may be supported and/or used, which are
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* represented using bits in the modifier. Not all combinations are valid,
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* and different devices or use-cases may support different combinations.
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*/
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#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
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/*
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* AFBC superblock size
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*
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* Indicates the superblock size(s) used for the AFBC buffer. The buffer
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* size (in pixels) must be aligned to a multiple of the superblock size.
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* Four lowest significant bits(LSBs) are reserved for block size.
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*/
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
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/*
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* AFBC lossless colorspace transform
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*
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* Indicates that the buffer makes use of the AFBC lossless colorspace
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* transform.
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*/
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#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
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/*
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* AFBC block-split
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*
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* Indicates that the payload of each superblock is split. The second
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* half of the payload is positioned at a predefined offset from the start
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* of the superblock payload.
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*/
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#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
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/*
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* AFBC sparse layout
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*
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* This flag indicates that the payload of each superblock must be stored at a
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* predefined position relative to the other superblocks in the same AFBC
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* buffer. This order is the same order used by the header buffer. In this mode
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* each superblock is given the same amount of space as an uncompressed
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* superblock of the particular format would require, rounding up to the next
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* multiple of 128 bytes in size.
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*/
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#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
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/*
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* AFBC copy-block restrict
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*
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* Buffers with this flag must obey the copy-block restriction. The restriction
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* is such that there are no copy-blocks referring across the border of 8x8
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* blocks. For the subsampled data the 8x8 limitation is also subsampled.
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*/
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#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
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/*
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* AFBC tiled layout
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*
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* The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
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* superblocks inside a tile are stored together in memory. 8x8 tiles are used
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* for pixel formats up to and including 32 bpp while 4x4 tiles are used for
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* larger bpp formats. The order between the tiles is scan line.
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* When the tiled layout is used, the buffer size (in pixels) must be aligned
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* to the tile size.
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*/
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#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
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/*
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* AFBC solid color blocks
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*
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* Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
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* can be reduced if a whole superblock is a single color.
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*/
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#define AFBC_FORMAT_MOD_SC (1ULL << 9)
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#if defined(__cplusplus)
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}
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#endif
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@ -46,6 +46,10 @@ extern "C" {
|
|||
#define DRM_MODE_TYPE_USERDEF (1<<5)
|
||||
#define DRM_MODE_TYPE_DRIVER (1<<6)
|
||||
|
||||
#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | \
|
||||
DRM_MODE_TYPE_USERDEF | \
|
||||
DRM_MODE_TYPE_DRIVER)
|
||||
|
||||
/* Video mode flags */
|
||||
/* bit compatible with the xrandr RR_ definitions (bits 0-13)
|
||||
*
|
||||
|
|
@ -89,6 +93,15 @@ extern "C" {
|
|||
#define DRM_MODE_PICTURE_ASPECT_NONE 0
|
||||
#define DRM_MODE_PICTURE_ASPECT_4_3 1
|
||||
#define DRM_MODE_PICTURE_ASPECT_16_9 2
|
||||
#define DRM_MODE_PICTURE_ASPECT_64_27 3
|
||||
#define DRM_MODE_PICTURE_ASPECT_256_135 4
|
||||
|
||||
/* Content type options */
|
||||
#define DRM_MODE_CONTENT_TYPE_NO_DATA 0
|
||||
#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1
|
||||
#define DRM_MODE_CONTENT_TYPE_PHOTO 2
|
||||
#define DRM_MODE_CONTENT_TYPE_CINEMA 3
|
||||
#define DRM_MODE_CONTENT_TYPE_GAME 4
|
||||
|
||||
/* Aspect ratio flag bitmask (4 bits 22:19) */
|
||||
#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)
|
||||
|
|
@ -98,6 +111,24 @@ extern "C" {
|
|||
(DRM_MODE_PICTURE_ASPECT_4_3<<19)
|
||||
#define DRM_MODE_FLAG_PIC_AR_16_9 \
|
||||
(DRM_MODE_PICTURE_ASPECT_16_9<<19)
|
||||
#define DRM_MODE_FLAG_PIC_AR_64_27 \
|
||||
(DRM_MODE_PICTURE_ASPECT_64_27<<19)
|
||||
#define DRM_MODE_FLAG_PIC_AR_256_135 \
|
||||
(DRM_MODE_PICTURE_ASPECT_256_135<<19)
|
||||
|
||||
#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | \
|
||||
DRM_MODE_FLAG_NHSYNC | \
|
||||
DRM_MODE_FLAG_PVSYNC | \
|
||||
DRM_MODE_FLAG_NVSYNC | \
|
||||
DRM_MODE_FLAG_INTERLACE | \
|
||||
DRM_MODE_FLAG_DBLSCAN | \
|
||||
DRM_MODE_FLAG_CSYNC | \
|
||||
DRM_MODE_FLAG_PCSYNC | \
|
||||
DRM_MODE_FLAG_NCSYNC | \
|
||||
DRM_MODE_FLAG_HSKEW | \
|
||||
DRM_MODE_FLAG_DBLCLK | \
|
||||
DRM_MODE_FLAG_CLKDIV2 | \
|
||||
DRM_MODE_FLAG_3D_MASK)
|
||||
|
||||
/* DPMS flags */
|
||||
/* bit compatible with the xorg definitions. */
|
||||
|
|
@ -155,8 +186,9 @@ extern "C" {
|
|||
/*
|
||||
* DRM_MODE_REFLECT_<axis>
|
||||
*
|
||||
* Signals that the contents of a drm plane is reflected in the <axis> axis,
|
||||
* Signals that the contents of a drm plane is reflected along the <axis> axis,
|
||||
* in the same way as mirroring.
|
||||
* See kerneldoc chapter "Plane Composition Properties" for more details.
|
||||
*
|
||||
* This define is provided as a convenience, looking up the property id
|
||||
* using the name->prop id lookup is the preferred method.
|
||||
|
|
@ -320,6 +352,7 @@ enum drm_mode_subconnector {
|
|||
#define DRM_MODE_CONNECTOR_VIRTUAL 15
|
||||
#define DRM_MODE_CONNECTOR_DSI 16
|
||||
#define DRM_MODE_CONNECTOR_DPI 17
|
||||
#define DRM_MODE_CONNECTOR_WRITEBACK 18
|
||||
|
||||
struct drm_mode_get_connector {
|
||||
|
||||
|
|
|
|||
|
|
@ -529,6 +529,28 @@ typedef struct drm_i915_irq_wait {
|
|||
*/
|
||||
#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
|
||||
|
||||
/*
|
||||
* Once upon a time we supposed that writes through the GGTT would be
|
||||
* immediately in physical memory (once flushed out of the CPU path). However,
|
||||
* on a few different processors and chipsets, this is not necessarily the case
|
||||
* as the writes appear to be buffered internally. Thus a read of the backing
|
||||
* storage (physical memory) via a different path (with different physical tags
|
||||
* to the indirect write via the GGTT) will see stale values from before
|
||||
* the GGTT write. Inside the kernel, we can for the most part keep track of
|
||||
* the different read/write domains in use (e.g. set-domain), but the assumption
|
||||
* of coherency is baked into the ABI, hence reporting its true state in this
|
||||
* parameter.
|
||||
*
|
||||
* Reports true when writes via mmap_gtt are immediately visible following an
|
||||
* lfence to flush the WCB.
|
||||
*
|
||||
* Reports false when writes via mmap_gtt are indeterminately delayed in an in
|
||||
* internal buffer and are _not_ immediately visible to third parties accessing
|
||||
* directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
|
||||
* communications channel when reporting false is strongly disadvised.
|
||||
*/
|
||||
#define I915_PARAM_MMAP_GTT_COHERENT 52
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
__s32 param;
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -24,7 +24,6 @@
|
|||
#ifndef QXL_DRM_H
|
||||
#define QXL_DRM_H
|
||||
|
||||
#include <stddef.h>
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
|
|
@ -89,7 +88,6 @@ struct drm_qxl_command {
|
|||
__u32 pad;
|
||||
};
|
||||
|
||||
/* XXX: call it drm_qxl_commands? */
|
||||
struct drm_qxl_execbuffer {
|
||||
__u32 flags; /* for future use */
|
||||
__u32 commands_num;
|
||||
|
|
|
|||
|
|
@ -32,143 +32,615 @@ extern "C" {
|
|||
#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
|
||||
#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_create {
|
||||
/**
|
||||
* @size:
|
||||
*
|
||||
* The size, in bytes, of the buffer object to be created.
|
||||
*/
|
||||
__u64 size;
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* A bitmask of flags that influence the creation of GEM objects:
|
||||
*
|
||||
* DRM_TEGRA_GEM_CREATE_TILED
|
||||
* Use the 16x16 tiling format for this buffer.
|
||||
*
|
||||
* DRM_TEGRA_GEM_CREATE_BOTTOM_UP
|
||||
* The buffer has a bottom-up layout.
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* The handle of the created GEM object. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_mmap {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle of the GEM object to obtain an mmap offset for.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* The mmap offset for the given GEM object. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_read {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to read the current value from.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The current syncpoint value. Set by the kernel upon successful
|
||||
* completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_incr {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to increment.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_wait {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to wait on.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @thresh:
|
||||
*
|
||||
* Threshold value for which to wait.
|
||||
*/
|
||||
__u32 thresh;
|
||||
|
||||
/**
|
||||
* @timeout:
|
||||
*
|
||||
* Timeout, in milliseconds, to wait.
|
||||
*/
|
||||
__u32 timeout;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The new syncpoint value after the wait. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_open_channel - parameters for the open channel IOCTL
|
||||
*/
|
||||
struct drm_tegra_open_channel {
|
||||
/**
|
||||
* @client:
|
||||
*
|
||||
* The client ID for this channel.
|
||||
*/
|
||||
__u32 client;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context of this channel. Set by the kernel upon
|
||||
* successful completion of the IOCTL. This context needs to be passed
|
||||
* to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
|
||||
*/
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_close_channel - parameters for the close channel IOCTL
|
||||
*/
|
||||
struct drm_tegra_close_channel {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context of this channel. This is obtained from the
|
||||
* DRM_TEGRA_OPEN_CHANNEL IOCTL.
|
||||
*/
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_get_syncpt {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying the channel for which to obtain
|
||||
* the syncpoint ID.
|
||||
*/
|
||||
__u64 context;
|
||||
|
||||
/**
|
||||
* @index:
|
||||
*
|
||||
* Index of the client syncpoint for which to obtain the ID.
|
||||
*/
|
||||
__u32 index;
|
||||
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* The ID of the given syncpoint. Set by the kernel upon successful
|
||||
* completion of the IOCTL.
|
||||
*/
|
||||
__u32 id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
|
||||
*/
|
||||
struct drm_tegra_get_syncpt_base {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying for which channel to obtain the
|
||||
* wait base.
|
||||
*/
|
||||
__u64 context;
|
||||
|
||||
/**
|
||||
* @syncpt:
|
||||
*
|
||||
* ID of the syncpoint for which to obtain the wait base.
|
||||
*/
|
||||
__u32 syncpt;
|
||||
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* The ID of the wait base corresponding to the client syncpoint. Set
|
||||
* by the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt - syncpoint increment operation
|
||||
*/
|
||||
struct drm_tegra_syncpt {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to operate on.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @incrs:
|
||||
*
|
||||
* Number of increments to perform for the syncpoint.
|
||||
*/
|
||||
__u32 incrs;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_cmdbuf - structure describing a command buffer
|
||||
*/
|
||||
struct drm_tegra_cmdbuf {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to a GEM object containing the command buffer.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* Offset, in bytes, into the GEM object identified by @handle at
|
||||
* which the command buffer starts.
|
||||
*/
|
||||
__u32 offset;
|
||||
|
||||
/**
|
||||
* @words:
|
||||
*
|
||||
* Number of 32-bit words in this command buffer.
|
||||
*/
|
||||
__u32 words;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_reloc - GEM object relocation structure
|
||||
*/
|
||||
struct drm_tegra_reloc {
|
||||
struct {
|
||||
/**
|
||||
* @cmdbuf.handle:
|
||||
*
|
||||
* Handle to the GEM object containing the command buffer for
|
||||
* which to perform this GEM object relocation.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @cmdbuf.offset:
|
||||
*
|
||||
* Offset, in bytes, into the command buffer at which to
|
||||
* insert the relocated address.
|
||||
*/
|
||||
__u32 offset;
|
||||
} cmdbuf;
|
||||
struct {
|
||||
/**
|
||||
* @target.handle:
|
||||
*
|
||||
* Handle to the GEM object to be relocated.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @target.offset:
|
||||
*
|
||||
* Offset, in bytes, into the target GEM object at which the
|
||||
* relocated data starts.
|
||||
*/
|
||||
__u32 offset;
|
||||
} target;
|
||||
|
||||
/**
|
||||
* @shift:
|
||||
*
|
||||
* The number of bits by which to shift relocated addresses.
|
||||
*/
|
||||
__u32 shift;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_waitchk - wait check structure
|
||||
*/
|
||||
struct drm_tegra_waitchk {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object containing a command stream on which to
|
||||
* perform the wait check.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* Offset, in bytes, of the location in the command stream to perform
|
||||
* the wait check on.
|
||||
*/
|
||||
__u32 offset;
|
||||
|
||||
/**
|
||||
* @syncpt:
|
||||
*
|
||||
* ID of the syncpoint to wait check.
|
||||
*/
|
||||
__u32 syncpt;
|
||||
|
||||
/**
|
||||
* @thresh:
|
||||
*
|
||||
* Threshold value for which to check.
|
||||
*/
|
||||
__u32 thresh;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_submit - job submission structure
|
||||
*/
|
||||
struct drm_tegra_submit {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying the channel to use for the
|
||||
* execution of this job.
|
||||
*/
|
||||
__u64 context;
|
||||
__u32 num_syncpts;
|
||||
__u32 num_cmdbufs;
|
||||
__u32 num_relocs;
|
||||
__u32 num_waitchks;
|
||||
__u32 waitchk_mask;
|
||||
__u32 timeout;
|
||||
__u64 syncpts;
|
||||
__u64 cmdbufs;
|
||||
__u64 relocs;
|
||||
__u64 waitchks;
|
||||
__u32 fence; /* Return value */
|
||||
|
||||
__u32 reserved[5]; /* future expansion */
|
||||
/**
|
||||
* @num_syncpts:
|
||||
*
|
||||
* The number of syncpoints operated on by this job. This defines the
|
||||
* length of the array pointed to by @syncpts.
|
||||
*/
|
||||
__u32 num_syncpts;
|
||||
|
||||
/**
|
||||
* @num_cmdbufs:
|
||||
*
|
||||
* The number of command buffers to execute as part of this job. This
|
||||
* defines the length of the array pointed to by @cmdbufs.
|
||||
*/
|
||||
__u32 num_cmdbufs;
|
||||
|
||||
/**
|
||||
* @num_relocs:
|
||||
*
|
||||
* The number of relocations to perform before executing this job.
|
||||
* This defines the length of the array pointed to by @relocs.
|
||||
*/
|
||||
__u32 num_relocs;
|
||||
|
||||
/**
|
||||
* @num_waitchks:
|
||||
*
|
||||
* The number of wait checks to perform as part of this job. This
|
||||
* defines the length of the array pointed to by @waitchks.
|
||||
*/
|
||||
__u32 num_waitchks;
|
||||
|
||||
/**
|
||||
* @waitchk_mask:
|
||||
*
|
||||
* Bitmask of valid wait checks.
|
||||
*/
|
||||
__u32 waitchk_mask;
|
||||
|
||||
/**
|
||||
* @timeout:
|
||||
*
|
||||
* Timeout, in milliseconds, before this job is cancelled.
|
||||
*/
|
||||
__u32 timeout;
|
||||
|
||||
/**
|
||||
* @syncpts:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_syncpt structures that
|
||||
* specify the syncpoint operations performed as part of this job.
|
||||
* The number of elements in the array must be equal to the value
|
||||
* given by @num_syncpts.
|
||||
*/
|
||||
__u64 syncpts;
|
||||
|
||||
/**
|
||||
* @cmdbufs:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_cmdbuf structures that
|
||||
* define the command buffers to execute as part of this job. The
|
||||
* number of elements in the array must be equal to the value given
|
||||
* by @num_syncpts.
|
||||
*/
|
||||
__u64 cmdbufs;
|
||||
|
||||
/**
|
||||
* @relocs:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_reloc structures that
|
||||
* specify the relocations that need to be performed before executing
|
||||
* this job. The number of elements in the array must be equal to the
|
||||
* value given by @num_relocs.
|
||||
*/
|
||||
__u64 relocs;
|
||||
|
||||
/**
|
||||
* @waitchks:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_waitchk structures that
|
||||
* specify the wait checks to be performed while executing this job.
|
||||
* The number of elements in the array must be equal to the value
|
||||
* given by @num_waitchks.
|
||||
*/
|
||||
__u64 waitchks;
|
||||
|
||||
/**
|
||||
* @fence:
|
||||
*
|
||||
* The threshold of the syncpoint associated with this job after it
|
||||
* has been completed. Set by the kernel upon successful completion of
|
||||
* the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
|
||||
* wait for this job to be finished.
|
||||
*/
|
||||
__u32 fence;
|
||||
|
||||
/**
|
||||
* @reserved:
|
||||
*
|
||||
* This field is reserved for future use. Must be 0.
|
||||
*/
|
||||
__u32 reserved[5];
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_set_tiling {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to set the tiling parameters.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @mode:
|
||||
*
|
||||
* The tiling mode to set. Must be one of:
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_PITCH
|
||||
* pitch linear format
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_TILED
|
||||
* 16x16 tiling format
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_BLOCK
|
||||
* 16Bx2 tiling format
|
||||
*/
|
||||
__u32 mode;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The value to set for the tiling mode parameter.
|
||||
*/
|
||||
__u32 value;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_get_tiling {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to query the tiling parameters.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @mode:
|
||||
*
|
||||
* The tiling mode currently associated with the GEM object. Set by
|
||||
* the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 mode;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The tiling mode parameter currently associated with the GEM object.
|
||||
* Set by the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
|
||||
#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_set_flags {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to set the flags.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* The flags to set for the GEM object.
|
||||
*/
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_get_flags {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to query the flags.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* The flags currently associated with the GEM object. Set by the
|
||||
* kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
|
|
@ -193,7 +665,7 @@ struct drm_tegra_gem_get_flags {
|
|||
#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
|
||||
#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
|
||||
#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
|
||||
#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
|
||||
#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
|
||||
#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
|
||||
|
|
|
|||
|
|
@ -183,10 +183,17 @@ struct drm_vc4_submit_cl {
|
|||
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
|
||||
__u32 perfmonid;
|
||||
|
||||
/* Unused field to align this struct on 64 bits. Must be set to 0.
|
||||
* If one ever needs to add an u32 field to this struct, this field
|
||||
* can be used.
|
||||
/* Syncobj handle to wait on. If set, processing of this render job
|
||||
* will not start until the syncobj is signaled. 0 means ignore.
|
||||
*/
|
||||
__u32 in_sync;
|
||||
|
||||
/* Syncobj handle to export fence to. If set, the fence in the syncobj
|
||||
* will be replaced with a fence that signals upon completion of this
|
||||
* render job. 0 means ignore.
|
||||
*/
|
||||
__u32 out_sync;
|
||||
|
||||
__u32 pad2;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue