headers: sync drm_fourcc.h with airlied/drm-next
This adds a bunch of modifiers stuff, as well as a few new formats. Includes the following changes: ebbb0e5cfd2ceb1150b1 drm: add extern C guard for the UAPI headers b9fb2a21ac8058965a6b drm_fourcc: Document linear modifier af913418261d6d3e7a29 drm_fourcc: Fix DRM_FORMAT_MOD_LINEAR #define fd056f05b9fcba35b77e drm: add fourcc codes for 16bit R and RG 73f1a5858bf82f3bf232 drm/fourcc: add vivante tiled layout format modifiers ba2b5277dc52cc96944d drm: add RGB formats with separate alpha plane 5e91144dd702d068b22a drm/tegra: Add tiling FB modifiers Generated using `make headers_install` from airlied/drm-next at commit 2a1720376adda5ecf8e636fbfb05339c7dad1c55 Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>main
Eric Engestrom
parent
ce9e3ba6e2
commit
1b8db17779
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@ -26,6 +26,10 @@
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
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((__u32)(c) << 16) | ((__u32)(d) << 24))
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@ -37,10 +41,17 @@
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/* 8 bpp Red */
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#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
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/* 16 bpp Red */
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#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
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/* 16 bpp RG */
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#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
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#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
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/* 32 bpp RG */
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#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
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#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
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/* 8 bpp RGB */
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#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
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#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
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@ -102,6 +113,20 @@
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#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
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/*
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* 2 plane RGB + A
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* index 0 = RGB plane, same format as the corresponding non _A8 format has
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* index 1 = A plane, [7:0] A
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*/
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#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
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#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
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#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
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#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
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#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
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#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
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#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
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#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
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/*
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* 2 plane YCbCr
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* index 0 = Y plane, [7:0] Y
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@ -150,11 +175,13 @@
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/* Vendor Ids: */
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#define DRM_FORMAT_MOD_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
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#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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#define DRM_FORMAT_MOD_VENDOR_NV 0x03
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#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
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#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
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#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
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/* add more to the end as needed */
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#define fourcc_mod_code(vendor, val) \
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@ -168,6 +195,16 @@
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* authoritative source for all of these.
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*/
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/*
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* Linear Layout
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*
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* Just plain linear layout. Note that this is different from no specifying any
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* modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
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* which tells the driver to also take driver-internal information into account
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* and so might actually result in a tiled framebuffer.
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*/
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#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
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/* Intel framebuffer modifiers */
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/*
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@ -229,4 +266,93 @@
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
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/* Vivante framebuffer modifiers */
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/*
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* Vivante 4x4 tiling layout
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*
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* This is a simple tiled layout using tiles of 4x4 pixels in a row-major
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* layout.
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*/
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#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
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/*
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* Vivante 64x64 super-tiling layout
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*
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* This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
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* contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
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* major layout.
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*
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* For more information: see
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* https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
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*/
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#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
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/*
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* Vivante 4x4 tiling layout for dual-pipe
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*
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* Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
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* different base address. Offsets from the base addresses are therefore halved
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* compared to the non-split tiled layout.
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*/
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#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
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/*
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* Vivante 64x64 super-tiling layout for dual-pipe
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*
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* Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
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* starts at a different base address. Offsets from the base addresses are
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* therefore halved compared to the non-split super-tiled layout.
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*/
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#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
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/* NVIDIA Tegra frame buffer modifiers */
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/*
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* Some modifiers take parameters, for example the number of vertical GOBs in
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* a block. Reserve the lower 32 bits for parameters
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*/
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#define __fourcc_mod_tegra_mode_shift 32
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#define fourcc_mod_tegra_code(val, params) \
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fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
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#define fourcc_mod_tegra_mod(m) \
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(m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
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#define fourcc_mod_tegra_param(m) \
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(m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
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/*
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* Tegra Tiled Layout, used by Tegra 2, 3 and 4.
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*
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* Pixels are arranged in simple tiles of 16 x 16 bytes.
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*/
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#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
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/*
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* Tegra 16Bx2 Block Linear layout, used by TK1/TX1
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*
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* Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
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* vertically by a power of 2 (1 to 32 GOBs) to form a block.
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*
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* Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
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*
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* Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
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* Valid values are:
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*
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* 0 == ONE_GOB
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* 1 == TWO_GOBS
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* 2 == FOUR_GOBS
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* 3 == EIGHT_GOBS
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* 4 == SIXTEEN_GOBS
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* 5 == THIRTYTWO_GOBS
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*
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* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
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* in full detail.
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*/
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#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
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#if defined(__cplusplus)
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}
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#endif
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#endif /* DRM_FOURCC_H */
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