radeon: pull bus master enable into its own function
parent
653b16f2dd
commit
1c817cc3fc
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@ -93,7 +93,6 @@ int radeon_resume(struct drm_device *dev)
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb;
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int i;
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u32 tmp;
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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return 0;
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@ -104,10 +103,7 @@ int radeon_resume(struct drm_device *dev)
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return -1;
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/* Turn on bus mastering -todo fix properly */
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if (dev_priv->chip_family < CHIP_RV380) {
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tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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RADEON_WRITE(RADEON_BUS_CNTL, tmp);
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}
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radeon_enable_bm(dev_priv);
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DRM_ERROR("\n");
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/* on atom cards re init the whole card
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@ -194,6 +194,23 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
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}
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}
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void radeon_enable_bm(struct drm_radeon_private *dev_priv)
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{
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u32 tmp;
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/* Turn on bus mastering */
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if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
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/* rs400, rs690/rs740 */
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tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS;
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RADEON_WRITE(RADEON_BUS_CNTL, tmp);
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} else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) {
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/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
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tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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RADEON_WRITE(RADEON_BUS_CNTL, tmp);
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} /* PCIE cards appears to not need this */
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}
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void radeon_pll_errata_after_index(struct drm_radeon_private *dev_priv)
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{
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@ -686,7 +703,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
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drm_radeon_private_t * dev_priv)
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{
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u32 ring_start, cur_read_ptr;
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u32 tmp;
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/* Initialize the memory controller. With new memory map, the fb location
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* is not changed, it should have been properly initialized already. Part
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@ -796,9 +812,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
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else
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RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x1f);
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/* Turn on bus mastering */
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tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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RADEON_WRITE(RADEON_BUS_CNTL, tmp);
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radeon_enable_bm(dev_priv);
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dev_priv->scratch[0] = 0;
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RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
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@ -1691,7 +1691,7 @@ extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *
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extern int radeon_cs_init(struct drm_device *dev);
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void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
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void radeon_init_memory_map(struct drm_device *dev);
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void radeon_enable_bm(struct drm_radeon_private *dev_priv);
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#define MARK_SAFE 1
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#define MARK_CHECK_OFFSET 2
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