add read/write 16
parent
b1cf4ca7e5
commit
1cec18a5cd
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@ -163,8 +163,10 @@ typedef void irqreturn_t;
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/* Read/write from bus space, with byteswapping to le if necessary */
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#define DRM_READ8(map, offset) *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset))
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#define DRM_READ16(map, offset) *(volatile u_int16_t *) (((unsigned long)(map)->handle) + (offset))
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#define DRM_READ32(map, offset) *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset))
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#define DRM_WRITE8(map, offset, val) *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset)) = val
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#define DRM_WRITE16(map, offset, val) *(volatile u_int16_t *) (((unsigned long)(map)->handle) + (offset)) = val
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#define DRM_WRITE32(map, offset, val) *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset)) = val
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/*
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#define DRM_READ8(map, offset) bus_space_read_1( (map)->iot, (map)->ioh, (offset) )
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@ -163,8 +163,10 @@ typedef void irqreturn_t;
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/* Read/write from bus space, with byteswapping to le if necessary */
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#define DRM_READ8(map, offset) *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset))
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#define DRM_READ16(map, offset) *(volatile u_int16_t *) (((unsigned long)(map)->handle) + (offset))
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#define DRM_READ32(map, offset) *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset))
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#define DRM_WRITE8(map, offset, val) *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset)) = val
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#define DRM_WRITE16(map, offset, val) *(volatile u_int16_t *) (((unsigned long)(map)->handle) + (offset)) = val
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#define DRM_WRITE32(map, offset, val) *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset)) = val
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/*
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#define DRM_READ8(map, offset) bus_space_read_1( (map)->iot, (map)->ioh, (offset) )
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