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do a TCL state flush before accessing VAP_CNTL to prevent lockups on r200 when enabling/disabling vertex programs

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Roland Scheidegger 2006-09-20 19:44:57 +02:00
parent ef98a8e20d
commit 1f71b8d7a4
1 changed files with 8 additions and 1 deletions
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9
shared-core/radeon_state.c
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@ -174,6 +174,14 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
} }
break; break;
case R200_EMIT_VAP_CTL: {
RING_LOCALS;
BEGIN_RING(2);
OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
ADVANCE_RING();
}
break;
case RADEON_EMIT_RB3D_COLORPITCH: case RADEON_EMIT_RB3D_COLORPITCH:
case RADEON_EMIT_RE_LINE_PATTERN: case RADEON_EMIT_RE_LINE_PATTERN:
case RADEON_EMIT_SE_LINE_WIDTH: case RADEON_EMIT_SE_LINE_WIDTH:
@ -201,7 +209,6 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
case R200_EMIT_TCL_LIGHT_MODEL_CTL_0: case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
case R200_EMIT_TFACTOR_0: case R200_EMIT_TFACTOR_0:
case R200_EMIT_VTX_FMT_0: case R200_EMIT_VTX_FMT_0:
case R200_EMIT_VAP_CTL:
case R200_EMIT_MATRIX_SELECT_0: case R200_EMIT_MATRIX_SELECT_0:
case R200_EMIT_TEX_PROC_CTL_2: case R200_EMIT_TEX_PROC_CTL_2:
case R200_EMIT_TCL_UCP_VERT_BLEND_CTL: case R200_EMIT_TCL_UCP_VERT_BLEND_CTL: