amdgpu: amdgpu_drm.h for new GPUVM fault ioctl
Based on agd5f/drm-next. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>main
Samuel Pitoiset
parent
6abc164052
commit
22b698a599
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@ -94,6 +94,9 @@ extern "C" {
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*
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* %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
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* for appending data.
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*
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* %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
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* signalling user mode queues.
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*/
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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@ -101,12 +104,14 @@ extern "C" {
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#define AMDGPU_GEM_DOMAIN_GDS 0x8
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#define AMDGPU_GEM_DOMAIN_GWS 0x10
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#define AMDGPU_GEM_DOMAIN_OA 0x20
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#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
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#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
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AMDGPU_GEM_DOMAIN_GTT | \
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AMDGPU_GEM_DOMAIN_VRAM | \
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AMDGPU_GEM_DOMAIN_GDS | \
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AMDGPU_GEM_DOMAIN_GWS | \
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AMDGPU_GEM_DOMAIN_OA)
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AMDGPU_GEM_DOMAIN_OA | \
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AMDGPU_GEM_DOMAIN_DOORBELL)
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/* Flag that CPU access will be required for the case of VRAM domain */
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#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
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@ -140,6 +145,32 @@ extern "C" {
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* not require GTT memory accounting
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*/
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#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
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/* Flag that BO can be discarded under memory pressure without keeping the
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* content.
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*/
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#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
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/* Flag that BO is shared coherently between multiple devices or CPU threads.
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* May depend on GPU instructions to flush caches to system scope explicitly.
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*
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* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
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* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
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*/
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#define AMDGPU_GEM_CREATE_COHERENT (1 << 13)
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/* Flag that BO should not be cached by GPU. Coherent without having to flush
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* GPU caches explicitly
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*
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* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
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* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
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*/
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#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
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/* Flag that BO should be coherent across devices when using device-level
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* atomics. May depend on GPU instructions to flush caches to device scope
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* explicitly, promoting them to system scope automatically.
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*
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* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
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* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
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*/
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#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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@ -218,15 +249,17 @@ union drm_amdgpu_bo_list {
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/* unknown cause */
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#define AMDGPU_CTX_UNKNOWN_RESET 3
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/* indicate gpu reset occured after ctx created */
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/* indicate gpu reset occurred after ctx created */
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#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
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/* indicate vram lost occured after ctx created */
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/* indicate vram lost occurred after ctx created */
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#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
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/* indicate some job from this context once cause gpu hang */
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#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
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/* indicate some errors are detected by RAS */
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#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
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#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
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/* indicate that the reset hasn't completed yet */
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#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)
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/* Context priority level */
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#define AMDGPU_CTX_PRIORITY_UNSET -2048
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@ -529,6 +562,8 @@ struct drm_amdgpu_gem_op {
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#define AMDGPU_VM_MTYPE_UC (4 << 5)
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/* Use Read Write MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_RW (5 << 5)
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/* don't allocate MALL */
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#define AMDGPU_VM_PAGE_NOALLOC (1 << 9)
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struct drm_amdgpu_gem_va {
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/** GEM object handle */
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@ -559,7 +594,8 @@ struct drm_amdgpu_gem_va {
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*/
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#define AMDGPU_HW_IP_VCN_ENC 7
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#define AMDGPU_HW_IP_VCN_JPEG 8
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#define AMDGPU_HW_IP_NUM 9
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#define AMDGPU_HW_IP_VPE 9
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#define AMDGPU_HW_IP_NUM 10
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#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
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@ -572,6 +608,7 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
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#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
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#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
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#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a
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struct drm_amdgpu_cs_chunk {
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__u32 chunk_id;
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@ -688,6 +725,15 @@ struct drm_amdgpu_cs_chunk_data {
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};
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};
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#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1
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struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
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__u64 shadow_va;
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__u64 csa_va;
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__u64 gds_va;
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__u64 flags;
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};
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/*
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* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
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*
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@ -695,6 +741,7 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_IDS_FLAGS_FUSION 0x1
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#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
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#define AMDGPU_IDS_FLAGS_TMZ 0x4
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#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
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/* indicate if acceleration can be working */
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#define AMDGPU_INFO_ACCEL_WORKING 0x00
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@ -747,6 +794,20 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_FW_DMCUB 0x14
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/* Subquery id: Query TOC firmware version */
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#define AMDGPU_INFO_FW_TOC 0x15
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/* Subquery id: Query CAP firmware version */
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#define AMDGPU_INFO_FW_CAP 0x16
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/* Subquery id: Query GFX RLCP firmware version */
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#define AMDGPU_INFO_FW_GFX_RLCP 0x17
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/* Subquery id: Query GFX RLCV firmware version */
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#define AMDGPU_INFO_FW_GFX_RLCV 0x18
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/* Subquery id: Query MES_KIQ firmware version */
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#define AMDGPU_INFO_FW_MES_KIQ 0x19
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/* Subquery id: Query MES firmware version */
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#define AMDGPU_INFO_FW_MES 0x1a
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/* Subquery id: Query IMU firmware version */
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#define AMDGPU_INFO_FW_IMU 0x1b
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/* Subquery id: Query VPE firmware version */
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#define AMDGPU_INFO_FW_VPE 0x1c
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/* number of bytes moved for TTM migration */
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#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
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@ -800,6 +861,10 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
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/* Subquery id: Query GPU stable pstate memory clock */
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#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
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/* Subquery id: Query GPU peak pstate shader clock */
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#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
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/* Subquery id: Query GPU peak pstate memory clock */
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#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
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/* Number of VRAM page faults on CPU access. */
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#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
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#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
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@ -839,6 +904,10 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
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/* Subquery id: Encode */
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#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
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/* Query the max number of IBs per gang per submission */
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#define AMDGPU_INFO_MAX_IBS 0x22
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/* query last page fault info */
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#define AMDGPU_INFO_GPUVM_FAULT 0x23
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@ -990,6 +1059,8 @@ struct drm_amdgpu_info_vbios {
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#define AMDGPU_VRAM_TYPE_DDR4 8
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#define AMDGPU_VRAM_TYPE_GDDR6 9
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#define AMDGPU_VRAM_TYPE_DDR5 10
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#define AMDGPU_VRAM_TYPE_LPDDR4 11
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#define AMDGPU_VRAM_TYPE_LPDDR5 12
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struct drm_amdgpu_info_device {
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/** PCI Device ID */
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@ -1015,7 +1086,8 @@ struct drm_amdgpu_info_device {
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__u32 enabled_rb_pipes_mask;
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__u32 num_rb_pipes;
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__u32 num_hw_gfx_contexts;
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__u32 _pad;
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/* PCIe version (the smaller of the GPU and the CPU/motherboard) */
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__u32 pcie_gen;
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__u64 ids_flags;
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/** Starting virtual address for UMDs. */
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__u64 virtual_address_offset;
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@ -1062,7 +1134,8 @@ struct drm_amdgpu_info_device {
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__u32 gs_prim_buffer_depth;
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/* max gs wavefront per vgt*/
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__u32 max_gs_waves_per_vgt;
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__u32 _pad1;
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/* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */
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__u32 pcie_num_lanes;
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/* always on cu bitmap */
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__u32 cu_ao_bitmap[4][4];
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/** Starting high virtual address for UMDs. */
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@ -1073,6 +1146,26 @@ struct drm_amdgpu_info_device {
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__u32 pa_sc_tile_steering_override;
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/* disabled TCCs */
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__u64 tcc_disabled_mask;
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__u64 min_engine_clock;
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__u64 min_memory_clock;
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/* The following fields are only set on gfx11+, older chips set 0. */
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__u32 tcp_cache_size; /* AKA GL0, VMEM cache */
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__u32 num_sqc_per_wgp;
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__u32 sqc_data_cache_size; /* AKA SMEM cache */
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__u32 sqc_inst_cache_size;
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__u32 gl1c_cache_size;
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__u32 gl2c_cache_size;
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__u64 mall_size; /* AKA infinity cache */
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/* high 32 bits of the rb pipes mask */
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__u32 enabled_rb_pipes_mask_hi;
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/* shadow area size for gfx11 */
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__u32 shadow_size;
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/* shadow area base virtual alignment for gfx11 */
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__u32 shadow_alignment;
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/* context save area size for gfx11 */
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__u32 csa_size;
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/* context save area base virtual alignment for gfx11 */
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__u32 csa_alignment;
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};
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struct drm_amdgpu_info_hw_ip {
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@ -1087,7 +1180,8 @@ struct drm_amdgpu_info_hw_ip {
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__u32 ib_size_alignment;
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/** Bitmask of available rings. Bit 0 means ring 0, etc. */
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__u32 available_rings;
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__u32 _pad;
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/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
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__u32 ip_discovery_version;
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};
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struct drm_amdgpu_info_num_handles {
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@ -1139,6 +1233,20 @@ struct drm_amdgpu_info_video_caps {
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struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
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};
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#define AMDGPU_VMHUB_TYPE_MASK 0xff
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#define AMDGPU_VMHUB_TYPE_SHIFT 0
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#define AMDGPU_VMHUB_TYPE_GFX 0
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#define AMDGPU_VMHUB_TYPE_MM0 1
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#define AMDGPU_VMHUB_TYPE_MM1 2
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#define AMDGPU_VMHUB_IDX_MASK 0xff00
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#define AMDGPU_VMHUB_IDX_SHIFT 8
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struct drm_amdgpu_info_gpuvm_fault {
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__u64 addr;
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__u32 status;
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__u32 vmhub;
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};
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/*
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* Supported GPU families
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*/
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@ -1152,7 +1260,12 @@ struct drm_amdgpu_info_video_caps {
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#define AMDGPU_FAMILY_RV 142 /* Raven */
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#define AMDGPU_FAMILY_NV 143 /* Navi10 */
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#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
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#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */
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#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
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#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
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#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
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#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
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#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
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#if defined(__cplusplus)
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}
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