i915: add backwards compat chipset flushing code
parent
c106a7d8b9
commit
2489062a33
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@ -19,7 +19,7 @@ r128-objs := r128_drv.o r128_cce.o r128_state.o r128_irq.o
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mga-objs := mga_drv.o mga_dma.o mga_state.o mga_warp.o mga_irq.o
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i810-objs := i810_drv.o i810_dma.o
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i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_fence.o \
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i915_buffer.o
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i915_buffer.o i915_compat.o
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nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \
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nouveau_object.o nouveau_irq.o nouveau_notifier.o nouveau_swmthd.o \
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nouveau_sgdma.o nouveau_dma.o \
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@ -0,0 +1,141 @@
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#include "drmP.h"
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
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#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
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#define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
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#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
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#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
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#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
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#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
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#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
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#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
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#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
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#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
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#define IS_I965 (agp_dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
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agp_dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
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agp_dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
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agp_dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
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agp_dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
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agp_dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
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#define IS_G33 (agp_dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
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agp_dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
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agp_dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
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#define I915_IFPADDR 0x60
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#define I965_IFPADDR 0x70
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static struct _intel_private_compat {
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void __iomem *flush_page;
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struct resource ifp_resource;
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} intel_private;
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static void
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intel_compat_align_resource(void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return;
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}
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static int intel_alloc_chipset_flush_resource(struct pci_dev *pdev)
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{
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int ret;
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ret = pci_bus_alloc_resource(pdev->bus, &intel_private.ifp_resource, PAGE_SIZE,
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PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
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intel_compat_align_resource, pdev);
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if (ret != 0)
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return ret;
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return 0;
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}
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static void intel_i915_setup_chipset_flush(struct pci_dev *pdev)
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{
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int ret;
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u32 temp;
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pci_read_config_dword(pdev, I915_IFPADDR, &temp);
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if (!(temp & 0x1)) {
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intel_alloc_chipset_flush_resource(pdev);
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pci_write_config_dword(pdev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
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} else {
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temp &= ~1;
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intel_private.ifp_resource.start = temp;
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intel_private.ifp_resource.end = temp + PAGE_SIZE;
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ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
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if (ret) {
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intel_private.ifp_resource.start = 0;
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printk("Failed inserting resource into tree\n");
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}
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}
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}
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static void intel_i965_g33_setup_chipset_flush(struct pci_dev *pdev)
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{
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u32 temp_hi, temp_lo;
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int ret;
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pci_read_config_dword(pdev, I965_IFPADDR + 4, &temp_hi);
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pci_read_config_dword(pdev, I965_IFPADDR, &temp_lo);
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if (!(temp_lo & 0x1)) {
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intel_alloc_chipset_flush_resource(pdev);
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pci_write_config_dword(pdev, I965_IFPADDR + 4, (intel_private.ifp_resource.start >> 32));
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pci_write_config_dword(pdev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
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intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
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} else {
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u64 l64;
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temp_lo &= ~0x1;
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l64 = ((u64)temp_hi << 32) | temp_lo;
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intel_private.ifp_resource.start = l64;
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intel_private.ifp_resource.end = l64 + PAGE_SIZE;
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ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
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if (!ret) {
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intel_private.ifp_resource.start = 0;
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printk("Failed inserting resource into tree\n");
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}
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}
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}
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void intel_init_chipset_flush_compat(struct drm_device *dev)
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{
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struct pci_dev *agp_dev = dev->agp->agp_info.device;
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intel_private.ifp_resource.name = "GMCH IFPBAR";
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intel_private.ifp_resource.flags = IORESOURCE_MEM;
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/* Setup chipset flush for 915 */
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if (IS_I965 || IS_G33) {
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intel_i965_g33_setup_chipset_flush(agp_dev);
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} else {
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intel_i915_setup_chipset_flush(agp_dev);
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}
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if (intel_private.ifp_resource.start) {
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intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
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if (!intel_private.flush_page)
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printk("unable to ioremap flush page - no chipset flushing");
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}
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}
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void intel_fini_chipset_flush_compat(struct drm_device *dev)
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{
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iounmap(intel_private.flush_page);
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release_resource(&intel_private.ifp_resource);
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}
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void drm_agp_chipset_flush(struct drm_device *dev)
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{
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if (intel_private.flush_page)
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writel(1, intel_private.flush_page);
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}
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#endif
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@ -1317,6 +1317,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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ret = drm_addmap(dev, base, size, _DRM_REGISTERS, _DRM_KERNEL,
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&dev_priv->mmio_map);
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
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intel_init_chipset_flush_compat(dev);
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#endif
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return ret;
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}
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@ -1329,6 +1332,9 @@ int i915_driver_unload(struct drm_device *dev)
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drm_free(dev->dev_private, sizeof(drm_i915_private_t),
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DRM_MEM_DRIVER);
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
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intel_fini_chipset_flush_compat(dev);
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#endif
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return 0;
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}
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@ -313,6 +313,11 @@ extern int i915_move(struct drm_buffer_object *bo, int evict,
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void i915_flush_ttm(struct drm_ttm *ttm);
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#endif
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
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extern void intel_init_chipset_flush_compat(struct drm_device *dev);
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extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
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#endif
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#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
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#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
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#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
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