geemili
/
drm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

i915: add backwards compat chipset flushing code

main
Dave Airlie 2007-10-31 11:27:44 +11:00
parent c106a7d8b9
commit 2489062a33
4 changed files with 153 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
linux-core/Makefile.kernel
View File

@ -19,7 +19,7 @@ r128-objs := r128_drv.o r128_cce.o r128_state.o r128_irq.o
mga-objs := mga_drv.o mga_dma.o mga_state.o mga_warp.o mga_irq.o
i810-objs := i810_drv.o i810_dma.o
i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_fence.o \
i915_buffer.o
i915_buffer.o i915_compat.o
nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \
nouveau_object.o nouveau_irq.o nouveau_notifier.o nouveau_swmthd.o \
nouveau_sgdma.o nouveau_dma.o \

141
linux-core/i915_compat.c Normal file
View File

@ -0,0 +1,141 @@
#include "drmP.h"
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
#define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
#define IS_I965 (agp_dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
agp_dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
agp_dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
agp_dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
agp_dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
agp_dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
#define IS_G33 (agp_dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
agp_dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
agp_dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
#define I915_IFPADDR 0x60
#define I965_IFPADDR 0x70
static struct _intel_private_compat {
void __iomem *flush_page;
struct resource ifp_resource;
} intel_private;
static void
intel_compat_align_resource(void *data, struct resource *res,
resource_size_t size, resource_size_t align)
{
return;
}
static int intel_alloc_chipset_flush_resource(struct pci_dev *pdev)
{
int ret;
ret = pci_bus_alloc_resource(pdev->bus, &intel_private.ifp_resource, PAGE_SIZE,
PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
intel_compat_align_resource, pdev);
if (ret != 0)
return ret;
return 0;
}
static void intel_i915_setup_chipset_flush(struct pci_dev *pdev)
{
int ret;
u32 temp;
pci_read_config_dword(pdev, I915_IFPADDR, &temp);
if (!(temp & 0x1)) {
intel_alloc_chipset_flush_resource(pdev);
pci_write_config_dword(pdev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
} else {
temp &= ~1;
intel_private.ifp_resource.start = temp;
intel_private.ifp_resource.end = temp + PAGE_SIZE;
ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
if (ret) {
intel_private.ifp_resource.start = 0;
printk("Failed inserting resource into tree\n");
}
}
}
static void intel_i965_g33_setup_chipset_flush(struct pci_dev *pdev)
{
u32 temp_hi, temp_lo;
int ret;
pci_read_config_dword(pdev, I965_IFPADDR + 4, &temp_hi);
pci_read_config_dword(pdev, I965_IFPADDR, &temp_lo);
if (!(temp_lo & 0x1)) {
intel_alloc_chipset_flush_resource(pdev);
pci_write_config_dword(pdev, I965_IFPADDR + 4, (intel_private.ifp_resource.start >> 32));
pci_write_config_dword(pdev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
} else {
u64 l64;
temp_lo &= ~0x1;
l64 = ((u64)temp_hi << 32) | temp_lo;
intel_private.ifp_resource.start = l64;
intel_private.ifp_resource.end = l64 + PAGE_SIZE;
ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
if (!ret) {
intel_private.ifp_resource.start = 0;
printk("Failed inserting resource into tree\n");
}
}
}
void intel_init_chipset_flush_compat(struct drm_device *dev)
{
struct pci_dev *agp_dev = dev->agp->agp_info.device;
intel_private.ifp_resource.name = "GMCH IFPBAR";
intel_private.ifp_resource.flags = IORESOURCE_MEM;
/* Setup chipset flush for 915 */
if (IS_I965 || IS_G33) {
intel_i965_g33_setup_chipset_flush(agp_dev);
} else {
intel_i915_setup_chipset_flush(agp_dev);
}
if (intel_private.ifp_resource.start) {
intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
if (!intel_private.flush_page)
printk("unable to ioremap flush page - no chipset flushing");
}
}
void intel_fini_chipset_flush_compat(struct drm_device *dev)
{
iounmap(intel_private.flush_page);
release_resource(&intel_private.ifp_resource);
}
void drm_agp_chipset_flush(struct drm_device *dev)
{
if (intel_private.flush_page)
writel(1, intel_private.flush_page);
}
#endif

6
shared-core/i915_dma.c
View File

@ -1317,6 +1317,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
ret = drm_addmap(dev, base, size, _DRM_REGISTERS, _DRM_KERNEL,
&dev_priv->mmio_map);
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
intel_init_chipset_flush_compat(dev);
#endif
return ret;
}
@ -1329,6 +1332,9 @@ int i915_driver_unload(struct drm_device *dev)
drm_free(dev->dev_private, sizeof(drm_i915_private_t),
DRM_MEM_DRIVER);
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
intel_fini_chipset_flush_compat(dev);
#endif
return 0;
}

5
shared-core/i915_drv.h
View File

@ -313,6 +313,11 @@ extern int i915_move(struct drm_buffer_object *bo, int evict,
void i915_flush_ttm(struct drm_ttm *ttm);
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
extern void intel_init_chipset_flush_compat(struct drm_device *dev);
extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
#endif
#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))