parent
8d9a11c55c
commit
26076bf24a
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@ -39,6 +39,7 @@
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int radeon_no_wb;
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int radeon_no_wb;
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int radeon_dynclks = 1;
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int radeon_dynclks = 1;
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int radeon_r4xx_atom = 0;
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int radeon_r4xx_atom = 0;
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int radeon_agpmode = 0;
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MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers\n");
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MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers\n");
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module_param_named(no_wb, radeon_no_wb, int, 0444);
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module_param_named(no_wb, radeon_no_wb, int, 0444);
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@ -52,6 +53,10 @@ module_param_named(dynclks, radeon_dynclks, int, 0444);
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MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
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MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
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module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
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module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
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MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
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module_param_named(agpmode, radeon_agpmode, int, 0444);
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static int dri_library_name(struct drm_device * dev, char * buf)
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static int dri_library_name(struct drm_device * dev, char * buf)
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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@ -2334,7 +2334,6 @@ int radeon_modeset_cp_suspend(struct drm_device *dev)
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int radeon_modeset_cp_resume(struct drm_device *dev)
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int radeon_modeset_cp_resume(struct drm_device *dev)
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t tmp;
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radeon_do_wait_for_idle(dev_priv);
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radeon_do_wait_for_idle(dev_priv);
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#if __OS_HAS_AGP
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#if __OS_HAS_AGP
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@ -2358,6 +2357,95 @@ int radeon_modeset_cp_resume(struct drm_device *dev)
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return 0;
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return 0;
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}
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}
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#if __OS_HAS_AGP
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int radeon_modeset_agp_init(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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struct drm_agp_mode mode;
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struct drm_agp_info info;
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int ret;
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int default_mode;
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uint32_t agp_status;
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bool is_v3;
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/* Acquire AGP. */
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ret = drm_agp_acquire(dev);
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if (ret) {
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DRM_ERROR("Unable to acquire AGP: %d\n", ret);
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return ret;
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}
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ret = drm_agp_info(dev, &info);
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if (ret) {
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DRM_ERROR("Unable to get AGP info: %d\n", ret);
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return ret;
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}
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mode.mode = info.mode;
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agp_status = (RADEON_READ(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
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is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
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if (is_v3) {
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default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
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} else {
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if (agp_status & RADEON_AGP_4X_MODE) default_mode = 4;
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else if (agp_status & RADEON_AGP_2X_MODE) default_mode = 2;
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else default_mode = 1;
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}
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if (radeon_agpmode > 0) {
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if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
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(radeon_agpmode > (is_v3 ? 8 : 4)) ||
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(radeon_agpmode & (radeon_agpmode - 1))) {
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DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
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radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
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default_mode);
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radeon_agpmode = default_mode;
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}
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else
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DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
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} else
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radeon_agpmode = default_mode;
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mode.mode &= ~RADEON_AGP_MODE_MASK;
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if (is_v3) {
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switch(radeon_agpmode) {
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case 8:
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mode.mode |= RADEON_AGPv3_8X_MODE;
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break;
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case 4:
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default:
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mode.mode |= RADEON_AGPv3_4X_MODE;
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break;
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}
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} else {
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switch(radeon_agpmode) {
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case 4: mode.mode |= RADEON_AGP_4X_MODE;
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case 2: mode.mode |= RADEON_AGP_2X_MODE;
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case 1:
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default:
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mode.mode |= RADEON_AGP_1X_MODE;
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break;
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}
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}
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mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
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ret = drm_agp_enable(dev, mode);
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if (ret) {
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DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode);
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return ret;
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}
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/* workaround some hw issues */
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if (dev_priv->chip_family <= CHIP_R200) {
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RADEON_WRITE(RADEON_AGP_CNTL, RADEON_READ(RADEON_AGP_CNTL) | 0x000e0000);
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}
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return 0;
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}
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#endif
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int radeon_modeset_cp_init(struct drm_device *dev)
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int radeon_modeset_cp_init(struct drm_device *dev)
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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@ -2389,6 +2477,11 @@ int radeon_modeset_cp_init(struct drm_device *dev)
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dev_priv->new_memmap = true;
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dev_priv->new_memmap = true;
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r300_init_reg_flags(dev);
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r300_init_reg_flags(dev);
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#if __OS_HAS_AGP
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if (dev_priv->flags & RADEON_IS_AGP)
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radeon_modeset_agp_init(dev);
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#endif
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return radeon_modeset_cp_resume(dev);
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return radeon_modeset_cp_resume(dev);
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}
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}
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@ -2478,6 +2571,7 @@ int radeon_static_clocks_init(struct drm_device *dev)
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}
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}
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}
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}
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radeon_force_some_clocks(dev);
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radeon_force_some_clocks(dev);
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return 0;
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}
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}
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int radeon_driver_load(struct drm_device *dev, unsigned long flags)
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int radeon_driver_load(struct drm_device *dev, unsigned long flags)
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@ -2523,6 +2617,12 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
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DRM_DEBUG("%s card detected\n",
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DRM_DEBUG("%s card detected\n",
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((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
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((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
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if ((dev_priv->flags & RADEON_IS_AGP) && (radeon_agpmode == -1)) {
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DRM_INFO("Forcing AGP to PCI mode\n");
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dev_priv->flags &= ~RADEON_IS_AGP;
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}
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ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
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ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
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drm_get_resource_len(dev, 2), _DRM_REGISTERS,
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drm_get_resource_len(dev, 2), _DRM_REGISTERS,
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_DRM_DRIVER | _DRM_READ_ONLY, &dev_priv->mmio);
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_DRM_DRIVER | _DRM_READ_ONLY, &dev_priv->mmio);
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@ -459,6 +459,7 @@ extern int radeon_dynclks;
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extern int radeon_r4xx_atom;
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extern int radeon_r4xx_atom;
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extern struct drm_ioctl_desc radeon_ioctls[];
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extern struct drm_ioctl_desc radeon_ioctls[];
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extern int radeon_max_ioctl;
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extern int radeon_max_ioctl;
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extern int radeon_agpmode;
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/* Check whether the given hardware address is inside the framebuffer or the
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/* Check whether the given hardware address is inside the framebuffer or the
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* GART area.
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* GART area.
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