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fix radeon memory mapping from Ben Herrenschmidt

main
Dave Airlie 2005-12-16 08:02:17 +00:00
parent e7b0176584
commit 274fdf482b
2 changed files with 9 additions and 2 deletions
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10
shared-core/radeon_cp.c
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@ -1306,6 +1306,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
unsigned int mem_size;
DRM_DEBUG("\n");
if (init->is_pci && (dev_priv->flags & CHIP_IS_AGP))
@ -1502,8 +1504,12 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
+ dev_priv->fb_location) >> 10));
dev_priv->gart_size = init->gart_size;
dev_priv->gart_vm_start = dev_priv->fb_location
+ RADEON_READ(RADEON_CONFIG_APER_SIZE);
mem_size = RADEON_READ(RADEON_CONFIG_MEMSIZE);
if (mem_size == 0)
mem_size = 0x800000;
dev_priv->gart_vm_start = dev_priv->fb_location + mem_size;
#if __OS_HAS_AGP
if (dev_priv->flags & CHIP_IS_AGP)

1
shared-core/radeon_drv.h
View File

@ -364,6 +364,7 @@ extern int r300_do_cp_cmdbuf( drm_device_t* dev,
# define RADEON_PLL_WR_EN (1 << 7)
#define RADEON_CLOCK_CNTL_INDEX 0x0008
#define RADEON_CONFIG_APER_SIZE 0x0108
#define RADEON_CONFIG_MEMSIZE 0x00f8
#define RADEON_CRTC_OFFSET 0x0224
#define RADEON_CRTC_OFFSET_CNTL 0x0228
# define RADEON_CRTC_TILE_EN (1 << 15)