Merged texmem-0-0-1
parent
7e1a4bfab3
commit
285b1cdc39
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@ -162,7 +162,7 @@ typedef struct drm_r128_sarea {
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unsigned int last_dispatch;
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drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1];
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int tex_age[R128_NR_TEX_HEAPS];
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unsigned int tex_age[R128_NR_TEX_HEAPS];
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int ctx_owner;
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} drm_r128_sarea_t;
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@ -322,12 +322,6 @@ typedef struct {
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} drm_radeon_state_t;
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typedef struct {
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unsigned char next, prev;
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unsigned char in_use;
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int age;
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} drm_radeon_tex_region_t;
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typedef struct {
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/* The channel for communication of state information to the
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* kernel on firing a vertex buffer with either of the
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@ -350,8 +344,8 @@ typedef struct {
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unsigned int last_dispatch;
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unsigned int last_clear;
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drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
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int tex_age[RADEON_NR_TEX_HEAPS];
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drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
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unsigned int tex_age[RADEON_NR_TEX_HEAPS];
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int ctx_owner;
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int pfState; /* number of 3d windows (0,1,2ormore) */
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int pfCurrentPage; /* which buffer is being displayed? */
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@ -581,6 +581,7 @@ extern void radeon_do_release(drm_device_t *dev);
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#define RADEON_TXFORMAT_ARGB4444 5
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#define RADEON_TXFORMAT_ARGB8888 6
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#define RADEON_TXFORMAT_RGBA8888 7
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#define RADEON_TXFORMAT_Y8 8
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#define RADEON_TXFORMAT_VYUY422 10
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#define RADEON_TXFORMAT_YVYU422 11
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#define RADEON_TXFORMAT_DXT1 12
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@ -162,7 +162,7 @@ typedef struct drm_r128_sarea {
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unsigned int last_dispatch;
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drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1];
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int tex_age[R128_NR_TEX_HEAPS];
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unsigned int tex_age[R128_NR_TEX_HEAPS];
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int ctx_owner;
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} drm_r128_sarea_t;
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@ -322,12 +322,6 @@ typedef struct {
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} drm_radeon_state_t;
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typedef struct {
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unsigned char next, prev;
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unsigned char in_use;
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int age;
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} drm_radeon_tex_region_t;
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typedef struct {
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/* The channel for communication of state information to the
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* kernel on firing a vertex buffer with either of the
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@ -350,8 +344,8 @@ typedef struct {
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unsigned int last_dispatch;
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unsigned int last_clear;
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drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
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int tex_age[RADEON_NR_TEX_HEAPS];
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drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
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unsigned int tex_age[RADEON_NR_TEX_HEAPS];
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int ctx_owner;
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int pfState; /* number of 3d windows (0,1,2ormore) */
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int pfCurrentPage; /* which buffer is being displayed? */
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@ -581,6 +581,7 @@ extern void radeon_do_release(drm_device_t *dev);
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#define RADEON_TXFORMAT_ARGB4444 5
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#define RADEON_TXFORMAT_ARGB8888 6
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#define RADEON_TXFORMAT_RGBA8888 7
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#define RADEON_TXFORMAT_Y8 8
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#define RADEON_TXFORMAT_VYUY422 10
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#define RADEON_TXFORMAT_YVYU422 11
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#define RADEON_TXFORMAT_DXT1 12
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