tests/amdgpu: add gfx ring bad slow draw test
for gfx9 Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>main
Flora Cui
Marek Olšák
parent
5e1f6533a0
commit
31a6ec141a
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@ -481,6 +481,12 @@ static void amdgpu_disable_suites()
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"gfx ring bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE))
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fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
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/* This test was ran on GFX9 only */
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//if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
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if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
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"gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE))
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fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
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if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
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fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
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@ -240,6 +240,8 @@ void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip
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void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type);
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void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring,
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int hang);
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void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring);
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/**
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* Helper functions
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*/
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@ -358,7 +358,8 @@ static const uint32_t preamblecache_gfx9[] = {
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enum ps_type {
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PS_CONST,
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PS_TEX,
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PS_HANG
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PS_HANG,
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PS_HANG_SLOW
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};
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static const uint32_t ps_const_shader_gfx9[] = {
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@ -510,6 +511,21 @@ struct amdgpu_test_shader memcpy_cs_hang_slow_rv = {
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1
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};
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unsigned int memcpy_ps_hang_slow_ai_codes[] = {
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0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000,
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0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00,
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0x00400002, 0xbefe010e, 0xbf8c0f70, 0xbf800000,
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0xbf800000, 0xbf800000, 0xbf800000, 0xc400180f,
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0x03020100, 0xbf810000
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};
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struct amdgpu_test_shader memcpy_ps_hang_slow_ai = {
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memcpy_ps_hang_slow_ai_codes,
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7,
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2,
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9
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};
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int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
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unsigned alignment, unsigned heap, uint64_t alloc_flags,
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uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
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@ -2759,6 +2775,35 @@ void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32
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}
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}
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static int amdgpu_draw_load_ps_shader_hang_slow(uint32_t *ptr, int family)
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{
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struct amdgpu_test_shader *shader;
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int i, loop = 0x40000;
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switch (family) {
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case AMDGPU_FAMILY_AI:
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case AMDGPU_FAMILY_RV:
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shader = &memcpy_ps_hang_slow_ai;
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break;
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default:
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return -1;
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break;
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}
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memcpy(ptr, shader->shader, shader->header_length * sizeof(uint32_t));
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for (i = 0; i < loop; i++)
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memcpy(ptr + shader->header_length + shader->body_length * i,
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shader->shader + shader->header_length,
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shader->body_length * sizeof(uint32_t));
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memcpy(ptr + shader->header_length + shader->body_length * loop,
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shader->shader + shader->header_length + shader->body_length,
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shader->foot_length * sizeof(uint32_t));
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return 0;
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}
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static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type)
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{
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int i;
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@ -2846,7 +2891,8 @@ static int amdgpu_draw_init(uint32_t *ptr)
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}
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static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr,
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uint64_t dst_addr)
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uint64_t dst_addr,
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int hang_slow)
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{
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int i = 0;
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@ -2871,7 +2917,7 @@ static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr,
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ptr[i++] = 0x318;
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ptr[i++] = dst_addr >> 8;
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ptr[i++] = dst_addr >> 40;
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ptr[i++] = 0x7c01f;
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ptr[i++] = hang_slow ? 0x1ffc7ff : 0x7c01f;
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ptr[i++] = 0;
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ptr[i++] = 0x50438;
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ptr[i++] = 0x10140000;
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@ -2880,7 +2926,7 @@ static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr,
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/* mmCB_MRT0_EPITCH */
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ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
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ptr[i++] = 0x1e8;
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ptr[i++] = 0x1f;
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ptr[i++] = hang_slow ? 0x7ff : 0x1f;
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/* 0xA32B CB_COLOR1_BASE */
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ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
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@ -2906,7 +2952,7 @@ static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr,
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return i;
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}
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static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr)
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static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr, int hang_slow)
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{
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int i = 0;
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const uint32_t *cached_cmd_ptr;
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@ -2938,6 +2984,8 @@ static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr)
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cached_cmd_size = sizeof(cached_cmd_gfx9);
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memcpy(ptr + i, cached_cmd_ptr, cached_cmd_size);
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if (hang_slow)
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*(ptr + i + 12) = 0x8000800;
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i += cached_cmd_size/sizeof(uint32_t);
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return i;
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@ -2945,7 +2993,8 @@ static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr)
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static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr,
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int ps_type,
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uint64_t shader_addr)
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uint64_t shader_addr,
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int hang_slow)
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{
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int i = 0;
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@ -2987,8 +3036,8 @@ static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr,
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ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
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ptr[i++] = 0x4c;
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i += 2;
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ptr[i++] = 0x42000000;
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ptr[i++] = 0x42000000;
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ptr[i++] = hang_slow ? 0x45000000 : 0x42000000;
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ptr[i++] = hang_slow ? 0x45000000 : 0x42000000;
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ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
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ptr[i++] = 0x50;
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@ -3125,11 +3174,11 @@ void amdgpu_memset_draw(amdgpu_device_handle device_handle,
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i = 0;
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i += amdgpu_draw_init(ptr_cmd + i);
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i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst);
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i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 0);
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i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i);
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i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 0);
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i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs);
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i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs, 0);
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i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_ps);
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@ -3288,11 +3337,11 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
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i = 0;
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i += amdgpu_draw_init(ptr_cmd + i);
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i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst);
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i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 0);
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i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i);
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i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 0);
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i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs);
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i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs, 0);
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i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps);
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@ -3438,6 +3487,168 @@ static void amdgpu_draw_test(void)
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}
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}
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void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring)
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{
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amdgpu_context_handle context_handle;
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amdgpu_bo_handle bo_shader_ps, bo_shader_vs;
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amdgpu_bo_handle bo_dst, bo_src, bo_cmd, resources[5];
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void *ptr_shader_ps;
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void *ptr_shader_vs;
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volatile unsigned char *ptr_dst;
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unsigned char *ptr_src;
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uint32_t *ptr_cmd;
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uint64_t mc_address_dst, mc_address_src, mc_address_cmd;
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uint64_t mc_address_shader_ps, mc_address_shader_vs;
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amdgpu_va_handle va_shader_ps, va_shader_vs;
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amdgpu_va_handle va_dst, va_src, va_cmd;
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struct amdgpu_gpu_info gpu_info = {0};
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int i, r;
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int bo_size = 0x4000000;
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int bo_shader_ps_size = 0x400000;
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int bo_shader_vs_size = 4096;
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int bo_cmd_size = 4096;
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struct amdgpu_cs_request ibs_request = {0};
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struct amdgpu_cs_ib_info ib_info= {0};
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uint32_t hang_state, hangs, expired;
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amdgpu_bo_list_handle bo_list;
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struct amdgpu_cs_fence fence_status = {0};
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r = amdgpu_query_gpu_info(device_handle, &gpu_info);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&bo_cmd, (void **)&ptr_cmd,
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&mc_address_cmd, &va_cmd);
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CU_ASSERT_EQUAL(r, 0);
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memset(ptr_cmd, 0, bo_cmd_size);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_ps_size, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0,
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&bo_shader_ps, &ptr_shader_ps,
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&mc_address_shader_ps, &va_shader_ps);
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CU_ASSERT_EQUAL(r, 0);
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memset(ptr_shader_ps, 0, bo_shader_ps_size);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_vs_size, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0,
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&bo_shader_vs, &ptr_shader_vs,
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&mc_address_shader_vs, &va_shader_vs);
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CU_ASSERT_EQUAL(r, 0);
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memset(ptr_shader_vs, 0, bo_shader_vs_size);
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r = amdgpu_draw_load_ps_shader_hang_slow(ptr_shader_ps, gpu_info.family_id);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_draw_load_vs_shader(ptr_shader_vs);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0,
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&bo_src, (void **)&ptr_src,
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&mc_address_src, &va_src);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0,
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&bo_dst, (void **)&ptr_dst,
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&mc_address_dst, &va_dst);
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CU_ASSERT_EQUAL(r, 0);
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memset(ptr_src, 0x55, bo_size);
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i = 0;
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i += amdgpu_draw_init(ptr_cmd + i);
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i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 1);
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i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 1);
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i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX,
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mc_address_shader_vs, 1);
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i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps);
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ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 8);
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ptr_cmd[i++] = 0xc;
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ptr_cmd[i++] = mc_address_src >> 8;
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ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000;
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ptr_cmd[i++] = 0x1ffc7ff;
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ptr_cmd[i++] = 0x90500fac;
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ptr_cmd[i++] = 0xffe000;
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i += 3;
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ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
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ptr_cmd[i++] = 0x14;
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ptr_cmd[i++] = 0x92;
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i += 3;
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ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
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ptr_cmd[i++] = 0x191;
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ptr_cmd[i++] = 0;
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i += amdgpu_draw_draw(ptr_cmd + i);
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while (i & 7)
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ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
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resources[0] = bo_dst;
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resources[1] = bo_src;
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resources[2] = bo_shader_ps;
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resources[3] = bo_shader_vs;
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resources[4] = bo_cmd;
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r = amdgpu_bo_list_create(device_handle, 5, resources, NULL, &bo_list);
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CU_ASSERT_EQUAL(r, 0);
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ib_info.ib_mc_address = mc_address_cmd;
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ib_info.size = i;
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ibs_request.ip_type = AMDGPU_HW_IP_GFX;
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ibs_request.ring = ring;
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ibs_request.resources = bo_list;
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ibs_request.number_of_ibs = 1;
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ibs_request.ibs = &ib_info;
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ibs_request.fence_info.handle = NULL;
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r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
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CU_ASSERT_EQUAL(r, 0);
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fence_status.ip_type = AMDGPU_HW_IP_GFX;
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fence_status.ip_instance = 0;
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fence_status.ring = ring;
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fence_status.context = context_handle;
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fence_status.fence = ibs_request.seq_no;
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/* wait for IB accomplished */
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r = amdgpu_cs_query_fence_status(&fence_status,
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AMDGPU_TIMEOUT_INFINITE,
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0, &expired);
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r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs);
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CU_ASSERT_EQUAL(r, 0);
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CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET);
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r = amdgpu_bo_list_destroy(bo_list);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_src, va_src, mc_address_src, bo_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_ps_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_shader_vs, va_shader_vs, mc_address_shader_vs, bo_shader_vs_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_ctx_free(context_handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void amdgpu_gpu_reset_test(void)
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{
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int r;
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@ -119,6 +119,7 @@ static void amdgpu_dispatch_hang_compute(void);
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static void amdgpu_dispatch_hang_slow_gfx(void);
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static void amdgpu_dispatch_hang_slow_compute(void);
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static void amdgpu_draw_hang_gfx(void);
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static void amdgpu_draw_hang_slow_gfx(void);
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CU_BOOL suite_deadlock_tests_enable(void)
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{
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@ -188,6 +189,7 @@ CU_TestInfo deadlock_tests[] = {
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{ "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_slow_gfx },
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{ "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute },
|
||||
{ "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_gfx },
|
||||
{ "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_slow_gfx },
|
||||
CU_TEST_INFO_NULL,
|
||||
};
|
||||
|
||||
|
|
@ -526,3 +528,19 @@ static void amdgpu_draw_hang_gfx(void)
|
|||
amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void amdgpu_draw_hang_slow_gfx(void)
|
||||
{
|
||||
struct drm_amdgpu_info_hw_ip info;
|
||||
uint32_t ring_id;
|
||||
int r;
|
||||
|
||||
r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
|
||||
amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
|
||||
amdgpu_memcpy_draw_hang_slow_test(device_handle, ring_id);
|
||||
amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue