radeon: overhaul ring interactions
emit in 16-dword blocks, emit irqs at same time as everything elsemain
parent
ce2cd141c3
commit
31b8a640db
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@ -170,10 +170,12 @@ void radeon_emit_copy_blit(struct drm_device * dev,
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ADVANCE_RING();
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}
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BEGIN_RING(4);
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BEGIN_RING(6);
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OUT_RING(CP_PACKET0(RADEON_RB2D_DSTCACHE_CTLSTAT, 0));
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OUT_RING(RADEON_RB2D_DC_FLUSH_ALL);
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RADEON_WAIT_UNTIL_2D_IDLE();
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OUT_RING(CP_PACKET2());
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OUT_RING(CP_PACKET2());
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ADVANCE_RING();
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COMMIT_RING();
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@ -265,10 +267,14 @@ void radeon_emit_solid_fill(struct drm_device * dev,
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ADVANCE_RING();
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}
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BEGIN_RING(4);
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BEGIN_RING(8);
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OUT_RING(CP_PACKET0(RADEON_RB2D_DSTCACHE_CTLSTAT, 0));
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OUT_RING(RADEON_RB2D_DC_FLUSH_ALL);
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RADEON_WAIT_UNTIL_2D_IDLE();
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OUT_RING(CP_PACKET2());
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OUT_RING(CP_PACKET2());
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OUT_RING(CP_PACKET2());
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OUT_RING(CP_PACKET2());
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ADVANCE_RING();
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COMMIT_RING();
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@ -39,7 +39,6 @@ int radeon_fence_emit_sequence(struct drm_device *dev, uint32_t class,
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uint32_t *native_type)
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{
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struct drm_radeon_private *dev_priv = (struct drm_radeon_private *) dev->dev_private;
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RING_LOCALS;
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if (!dev_priv)
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return -EINVAL;
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@ -1086,7 +1086,7 @@ int radeon_gem_object_unpin(struct drm_gem_object *obj)
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#define RADEON_NUM_IB (RADEON_IB_MEMORY / RADEON_IB_SIZE)
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int radeon_gem_ib_get(struct drm_radeon_cs_parser *parser, uint32_t *card_offset)
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int radeon_gem_ib_get(struct drm_radeon_cs_parser *parser)
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{
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int i, index = -1;
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int ret;
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@ -1132,8 +1132,8 @@ int radeon_gem_ib_get(struct drm_radeon_cs_parser *parser, uint32_t *card_offset
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return -EINVAL;
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}
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*card_offset = dev_priv->gart_vm_start + dev_priv->ib_objs[index]->bo->offset;
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parser->ib = dev_priv->ib_objs[index]->kmap.virtual;
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parser->card_offset = dev_priv->gart_vm_start + dev_priv->ib_objs[index]->bo->offset;
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dev_priv->ib_alloc_bitmap |= (1 << i);
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return 0;
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}
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@ -1150,6 +1150,7 @@ static void radeon_gem_ib_free(struct drm_radeon_cs_parser *parser)
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if (dev_priv->ib_objs[i]->kmap.virtual == parser->ib) {
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/* emit a fence object */
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ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence);
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dev_priv->irq_emitted = 0;
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if (ret) {
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drm_putback_buffer_objects(dev);
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}
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@ -38,10 +38,8 @@ int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
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uint64_t *chunk_array;
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uint64_t *chunk_array_ptr;
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uint32_t card_offset;
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long size;
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int r, i;
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RING_LOCALS;
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/* set command stream id to 0 which is fake id */
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cs_id = 0;
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@ -144,7 +142,7 @@ int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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}
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/* get ib */
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r = dev_priv->cs.ib_get(&parser, &card_offset);
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r = dev_priv->cs.ib_get(&parser);
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if (r) {
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DRM_ERROR("ib_get failed\n");
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goto out;
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@ -156,16 +154,8 @@ int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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goto out;
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}
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BEGIN_RING(4);
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OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
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OUT_RING(card_offset);
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OUT_RING(parser.chunks[parser.ib_index].length_dw);
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OUT_RING(CP_PACKET2());
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ADVANCE_RING();
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/* emit cs id sequence */
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dev_priv->cs.id_emit(dev, &cs_id);
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COMMIT_RING();
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dev_priv->cs.id_emit(&parser, &cs_id);
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cs->cs_id = cs_id;
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@ -194,7 +184,6 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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long size;
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int r;
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struct drm_radeon_kernel_chunk chunk_fake[1];
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RING_LOCALS;
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/* set command stream id to 0 which is fake id */
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cs_id = 0;
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@ -237,7 +226,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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parser.reloc_index = -1;
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/* get ib */
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r = dev_priv->cs.ib_get(&parser, &card_offset);
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r = dev_priv->cs.ib_get(&parser);
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if (r) {
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goto out;
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}
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@ -248,15 +237,8 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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goto out;
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}
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BEGIN_RING(4);
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OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
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OUT_RING(card_offset);
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OUT_RING(cs->dwords);
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OUT_RING(CP_PACKET2());
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ADVANCE_RING();
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/* emit cs id sequence */
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dev_priv->cs.id_emit(dev, &cs_id);
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dev_priv->cs.id_emit(&parser, &cs_id);
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COMMIT_RING();
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cs->cs_id = cs_id;
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@ -518,37 +500,75 @@ uint32_t radeon_cs_id_get(struct drm_radeon_private *radeon)
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return (radeon->cs.id_scnt | radeon->cs.id_wcnt);
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}
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void r100_cs_id_emit(struct drm_device *dev, uint32_t *id)
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void r100_cs_id_emit(struct drm_radeon_cs_parser *parser, uint32_t *id)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = parser->dev->dev_private;
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RING_LOCALS;
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dev_priv->irq_emitted = radeon_update_breadcrumb(parser->dev);
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/* ISYNC_CNTL should have CPSCRACTH bit set */
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*id = radeon_cs_id_get(dev_priv);
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/* emit id in SCRATCH4 (not used yet in old drm) */
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BEGIN_RING(2);
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BEGIN_RING(10);
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OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
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OUT_RING(parser->card_offset);
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OUT_RING(parser->chunks[parser->ib_index].length_dw);
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OUT_RING(CP_PACKET2());
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OUT_RING(CP_PACKET0(RADEON_SCRATCH_REG4, 0));
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OUT_RING(*id);
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OUT_RING_REG(RADEON_LAST_SWI_REG, dev_priv->irq_emitted);
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OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
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ADVANCE_RING();
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COMMIT_RING();
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}
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void r300_cs_id_emit(struct drm_device *dev, uint32_t *id)
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void r300_cs_id_emit(struct drm_radeon_cs_parser *parser, uint32_t *id)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = parser->dev->dev_private;
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int i;
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RING_LOCALS;
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dev_priv->irq_emitted = radeon_update_breadcrumb(parser->dev);
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/* ISYNC_CNTL should not have CPSCRACTH bit set */
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*id = radeon_cs_id_get(dev_priv);
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/* emit id in SCRATCH6 */
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BEGIN_RING(8);
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OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 0));
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OUT_RING(6);
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OUT_RING(CP_PACKET0(R300_CP_RESYNC_DATA, 0));
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OUT_RING(*id);
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BEGIN_RING(16);
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OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
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OUT_RING(parser->card_offset);
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OUT_RING(parser->chunks[parser->ib_index].length_dw);
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OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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OUT_RING(R300_RB3D_DC_FINISH);
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RADEON_WAIT_UNTIL_3D_IDLE();
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OUT_RING(0);
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for (i = 0; i < 11; i++) /* emit fillers like fglrx */
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OUT_RING(CP_PACKET2());
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ADVANCE_RING();
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COMMIT_RING();
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BEGIN_RING(16);
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OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH);
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OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
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OUT_RING(6);
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OUT_RING(*id);
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OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FINISH|R300_RB3D_DC_FLUSH);
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/* emit inline breadcrumb for TTM fencing */
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#if 1
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RADEON_WAIT_UNTIL_3D_IDLE();
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OUT_RING_REG(RADEON_LAST_SWI_REG, dev_priv->irq_emitted);
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#else
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OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
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OUT_RING(3); /* breadcrumb register */
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OUT_RING(dev_priv->irq_emitted);
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OUT_RING(CP_PACKET2());
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#endif
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OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
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OUT_RING(CP_PACKET2());
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OUT_RING(CP_PACKET2());
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OUT_RING(CP_PACKET2());
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ADVANCE_RING();
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COMMIT_RING();
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}
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uint32_t r100_cs_id_last_get(struct drm_device *dev)
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@ -308,6 +308,7 @@ struct drm_radeon_cs_parser {
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struct drm_radeon_kernel_chunk *chunks;
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int ib_index;
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int reloc_index;
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uint32_t card_offset;
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void *ib;
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};
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@ -319,12 +320,12 @@ struct drm_radeon_cs_priv {
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uint32_t id_last_scnt;
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int (*parse)(struct drm_radeon_cs_parser *parser);
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void (*id_emit)(struct drm_device *dev, uint32_t *id);
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void (*id_emit)(struct drm_radeon_cs_parser *parser, uint32_t *id);
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uint32_t (*id_last_get)(struct drm_device *dev);
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/* this ib handling callback are for hidding memory manager drm
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* from memory manager less drm, free have to emit ib discard
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* sequence into the ring */
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int (*ib_get)(struct drm_radeon_cs_parser *parser, uint32_t *card_offset);
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int (*ib_get)(struct drm_radeon_cs_parser *parser);
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uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
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void (*ib_free)(struct drm_radeon_cs_parser *parser);
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/* do a relocation either MM or non-MM */
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@ -459,6 +460,7 @@ typedef struct drm_radeon_private {
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struct drm_radeon_cs_priv cs;
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struct radeon_pm_regs pmregs;
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int irq_emitted;
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atomic_t irq_received;
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} drm_radeon_private_t;
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@ -223,8 +223,10 @@ int radeon_emit_irq(struct drm_device * dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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unsigned int ret;
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int i;
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RING_LOCALS;
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if (!dev_priv->irq_emitted) {
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ret = radeon_update_breadcrumb(dev);
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BEGIN_RING(4);
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@ -232,6 +234,8 @@ int radeon_emit_irq(struct drm_device * dev)
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OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
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ADVANCE_RING();
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COMMIT_RING();
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} else
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ret = dev_priv->irq_emitted;
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return ret;
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}
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