intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
In specific, any resource used with flat/heapless (0x00000000-0xfffff000)
General State Heap (GSH) or Instruction State Heap (ISH) must be in a
32-bit range, because the General State Offset and Instruction State Offset
are limited to 32-bits.
The i915 driver has been modified to provide a flag to set when the 4GB
limit is not necessary in a given bo (EXEC_OBJECT_SUPPORTS_48B_ADDRESS).
48-bit range will only be used when explicitly requested.
Callers to the existing drm_intel_bo_emit_reloc function should set the
use_48b_address_range flag beforehand, in order to use full ppgtt range.
v2: Make set/clear functions nops on pre-gen8 platforms, and use them
internally in emit_reloc functions (Ben)
s/48BADDRESS/48B_ADDRESS/ (Dave)
v3: Keep set/clear functions internal, no-one needs to use them directly.
v4: Don't set 48bit-support flag in emit reloc, check for ppgtt type
before enabling set/clear function, print full offsets in debug
statements, using port of lower_32_bits and upper_32_bits from linux
kernel (Michał)
References: http://lists.freedesktop.org/archives/intel-gfx/2015-July/072612.html
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
main
Michel Thierry
Kristian Høgsberg Kristensen
parent
7d74a83d22
commit
3350add5cc
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@ -292,6 +292,17 @@ drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
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return -1;
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}
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int
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drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
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{
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if (bo->bufmgr->bo_use_48b_address_range) {
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bo->bufmgr->bo_use_48b_address_range(bo, enable);
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return 0;
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}
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return -ENODEV;
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}
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int
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drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
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{
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@ -164,6 +164,7 @@ int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
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int drm_intel_bo_busy(drm_intel_bo *bo);
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int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
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int drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable);
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int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
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int drm_intel_bo_is_reusable(drm_intel_bo *bo);
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@ -83,6 +83,22 @@
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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#define MAX2(A, B) ((A) > (B) ? (A) : (B))
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/**
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* upper_32_bits - return bits 32-63 of a number
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* @n: the number we're accessing
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*
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* A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
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* the "right shift count >= width of type" warning when that quantity is
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* 32-bits.
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*/
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#define upper_32_bits(n) ((__u32)(((n) >> 16) >> 16))
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/**
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* lower_32_bits - return bits 0-31 of a number
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* @n: the number we're accessing
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*/
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#define lower_32_bits(n) ((__u32)(n))
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typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
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struct drm_intel_gem_bo_bucket {
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@ -236,6 +252,15 @@ struct _drm_intel_bo_gem {
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*/
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bool is_userptr;
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/**
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* Boolean of whether this buffer can be placed in the full 48-bit
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* address range on gen8+.
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*
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* By default, buffers will be keep in a 32-bit range, unless this
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* flag is explicitly set.
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*/
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bool use_48b_address_range;
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/**
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* Size in bytes of this buffer and its relocation descendents.
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*
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@ -400,14 +425,16 @@ drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
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drm_intel_bo_gem *target_gem =
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(drm_intel_bo_gem *) target_bo;
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DBG("%2d: %d (%s)@0x%08llx -> "
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"%d (%s)@0x%08lx + 0x%08x\n",
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DBG("%2d: %d (%s)@0x%08x %08x -> "
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"%d (%s)@0x%08x %08x + 0x%08x\n",
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i,
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bo_gem->gem_handle, bo_gem->name,
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(unsigned long long)bo_gem->relocs[j].offset,
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upper_32_bits(bo_gem->relocs[j].offset),
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lower_32_bits(bo_gem->relocs[j].offset),
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target_gem->gem_handle,
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target_gem->name,
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target_bo->offset64,
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upper_32_bits(target_bo->offset64),
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lower_32_bits(target_bo->offset64),
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bo_gem->relocs[j].delta);
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}
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}
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@ -473,11 +500,15 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
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drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
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drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
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int index;
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int flags = 0;
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if (need_fence)
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flags |= EXEC_OBJECT_NEEDS_FENCE;
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if (bo_gem->use_48b_address_range)
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flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
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if (bo_gem->validate_index != -1) {
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if (need_fence)
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bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
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EXEC_OBJECT_NEEDS_FENCE;
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bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |= flags;
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return;
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}
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@ -506,13 +537,9 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
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bufmgr_gem->exec2_objects[index].alignment = bo->align;
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bufmgr_gem->exec2_objects[index].offset = 0;
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bufmgr_gem->exec_bos[index] = bo;
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bufmgr_gem->exec2_objects[index].flags = 0;
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bufmgr_gem->exec2_objects[index].flags = flags;
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bufmgr_gem->exec2_objects[index].rsvd1 = 0;
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bufmgr_gem->exec2_objects[index].rsvd2 = 0;
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if (need_fence) {
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bufmgr_gem->exec2_objects[index].flags |=
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EXEC_OBJECT_NEEDS_FENCE;
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}
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bufmgr_gem->exec_count++;
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}
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@ -785,6 +812,7 @@ retry:
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bo_gem->used_as_reloc_target = false;
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bo_gem->has_error = false;
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bo_gem->reusable = true;
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bo_gem->use_48b_address_range = false;
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drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, alignment);
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@ -931,6 +959,7 @@ drm_intel_gem_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
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bo_gem->used_as_reloc_target = false;
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bo_gem->has_error = false;
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bo_gem->reusable = false;
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bo_gem->use_48b_address_range = false;
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drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
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@ -1086,6 +1115,7 @@ drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
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bo_gem->bo.handle = open_arg.handle;
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bo_gem->global_name = handle;
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bo_gem->reusable = false;
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bo_gem->use_48b_address_range = false;
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memclear(get_tiling);
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get_tiling.handle = bo_gem->gem_handle;
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@ -1935,6 +1965,13 @@ do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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return 0;
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}
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static void
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drm_intel_gem_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
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{
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drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
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bo_gem->use_48b_address_range = enable;
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}
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static int
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drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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drm_intel_bo *target_bo, uint32_t target_offset,
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@ -2078,10 +2115,12 @@ drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
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/* Update the buffer offset */
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if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
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DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
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bo_gem->gem_handle, bo_gem->name, bo->offset64,
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(unsigned long long)bufmgr_gem->exec_objects[i].
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offset);
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DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n",
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bo_gem->gem_handle, bo_gem->name,
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upper_32_bits(bo->offset64),
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lower_32_bits(bo->offset64),
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upper_32_bits(bufmgr_gem->exec_objects[i].offset),
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lower_32_bits(bufmgr_gem->exec_objects[i].offset));
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bo->offset64 = bufmgr_gem->exec_objects[i].offset;
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bo->offset = bufmgr_gem->exec_objects[i].offset;
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}
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@ -2099,9 +2138,12 @@ drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
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/* Update the buffer offset */
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if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
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DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
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bo_gem->gem_handle, bo_gem->name, bo->offset64,
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(unsigned long long)bufmgr_gem->exec2_objects[i].offset);
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DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n",
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bo_gem->gem_handle, bo_gem->name,
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upper_32_bits(bo->offset64),
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lower_32_bits(bo->offset64),
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upper_32_bits(bufmgr_gem->exec2_objects[i].offset),
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lower_32_bits(bufmgr_gem->exec2_objects[i].offset));
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bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
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bo->offset = bufmgr_gem->exec2_objects[i].offset;
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}
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@ -2486,6 +2528,7 @@ drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int s
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bo_gem->used_as_reloc_target = false;
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bo_gem->has_error = false;
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bo_gem->reusable = false;
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bo_gem->use_48b_address_range = false;
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DRMINITLISTHEAD(&bo_gem->vma_list);
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DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
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@ -3283,6 +3326,13 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
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}
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}
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if (bufmgr_gem->gen >= 8) {
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gp.param = I915_PARAM_HAS_ALIASING_PPGTT;
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ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
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if (ret == 0 && *gp.value == 3)
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bufmgr_gem->bufmgr.bo_use_48b_address_range = drm_intel_gem_bo_use_48b_address_range;
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}
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/* Let's go with one relocation per every 2 dwords (but round down a bit
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* since a power of two will mean an extra page allocation for the reloc
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* buffer).
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@ -151,6 +151,20 @@ struct _drm_intel_bufmgr {
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*/
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void (*destroy) (drm_intel_bufmgr *bufmgr);
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/**
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* Indicate if the buffer can be placed anywhere in the full ppgtt
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* address range (2^48).
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*
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* Any resource used with flat/heapless (0x00000000-0xfffff000)
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* General State Heap (GSH) or Intructions State Heap (ISH) must
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* be in a 32-bit range. 48-bit range will only be used when explicitly
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* requested.
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*
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* \param bo Buffer to set the use_48b_address_range flag.
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* \param enable The flag value.
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*/
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void (*bo_use_48b_address_range) (drm_intel_bo *bo, uint32_t enable);
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/**
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* Add relocation entry in reloc_buf, which will be updated with the
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* target buffer's real offset on on command submission.
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