radeon: add function to configure PCIE lanes
parent
e1e782af5d
commit
34af71c42a
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@ -178,3 +178,63 @@ int radeon_resume(struct drm_device *dev)
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return 0;
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}
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bool radeon_set_pcie_lanes(struct drm_device *dev, int lanes)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t link_width_cntl, mask;
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/* FIXME wait for idle */
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switch (lanes) {
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case 0:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
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break;
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case 1:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
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break;
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case 2:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
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break;
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case 4:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
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break;
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case 8:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
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break;
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case 12:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
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break;
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case 16:
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default:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
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break;
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}
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link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
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(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
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return true;
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link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
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RADEON_PCIE_LC_RECONFIG_NOW |
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RADEON_PCIE_LC_RECONFIG_LATER |
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RADEON_PCIE_LC_SHORT_RECONFIG_EN);
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link_width_cntl |= mask;
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RADEON_WRITE_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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RADEON_WRITE_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW);
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/* wait for lane set to complete */
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link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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while (link_width_cntl == 0xffffffff)
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link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
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(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
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return true;
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else
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return false;
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}
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@ -274,6 +274,24 @@
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#define RADEON_BUS_CNTL1 0x0034
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# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
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//#define RADEON_PCIE_INDEX 0x0030
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//#define RADEON_PCIE_DATA 0x0034
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#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
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# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
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# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
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# define RADEON_PCIE_LC_LINK_WIDTH_X0 0
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# define RADEON_PCIE_LC_LINK_WIDTH_X1 1
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# define RADEON_PCIE_LC_LINK_WIDTH_X2 2
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# define RADEON_PCIE_LC_LINK_WIDTH_X4 3
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# define RADEON_PCIE_LC_LINK_WIDTH_X8 4
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# define RADEON_PCIE_LC_LINK_WIDTH_X12 5
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# define RADEON_PCIE_LC_LINK_WIDTH_X16 6
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# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
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# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
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# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
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# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
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# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
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#define RADEON_CACHE_CNTL 0x1724
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#define RADEON_CACHE_LINE 0x0f0c /* PCI */
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#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
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@ -235,7 +235,7 @@ void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t da
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radeon_pll_errata_after_data(dev_priv);
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}
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static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
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u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
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{
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RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
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return RADEON_READ(RADEON_PCIE_DATA);
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@ -1298,6 +1298,7 @@ int radeon_resume(struct drm_device *dev);
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extern u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
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extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data);
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extern u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr);
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#define RADEON_WRITE_P(reg, val, mask) \
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do { \
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