radeon: fixup domains and use them properly
Dave Airlie
parent
4c8e8e0d0b
commit
361ab10d2f
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@ -82,16 +82,18 @@ struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size,
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int ret;
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uint32_t flags;
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DRM_DEBUG("size 0x%x, alignment %d, initial_domain %d\n", size, alignment, initial_domain);
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obj = drm_gem_object_alloc(dev, size);
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if (!obj)
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return NULL;;
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obj_priv = obj->driver_private;
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flags = DRM_BO_FLAG_MAPPABLE;
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if (initial_domain == RADEON_GEM_DOMAIN_VRAM)
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flags = DRM_BO_FLAG_MEM_VRAM | DRM_BO_FLAG_MAPPABLE;
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flags |= DRM_BO_FLAG_MEM_VRAM;
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else if (initial_domain == RADEON_GEM_DOMAIN_GTT)
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flags |= DRM_BO_FLAG_MEM_TT;
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else
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flags = DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_MAPPABLE;
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flags |= DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_CACHED;
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flags |= DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE;
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/* create a TTM BO */
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@ -102,6 +104,7 @@ struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size,
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if (ret)
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goto fail;
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DRM_DEBUG("%p : size 0x%x, alignment %d, initial_domain %d\n", obj_priv->bo, size, alignment, initial_domain);
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return obj;
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fail:
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@ -144,6 +147,55 @@ fail:
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return ret;
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}
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int radeon_gem_set_domain(struct drm_gem_object *obj, uint32_t read_domains, uint32_t write_domain, uint32_t *flags_p, bool unfenced)
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{
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struct drm_device *dev = obj->dev;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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struct drm_radeon_gem_object *obj_priv;
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uint32_t flags = 0;
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int ret;
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obj_priv = obj->driver_private;
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/* work out where to validate the buffer to */
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if (write_domain) { /* write domains always win */
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if (write_domain == RADEON_GEM_DOMAIN_VRAM)
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flags = DRM_BO_FLAG_MEM_VRAM;
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else if (write_domain == RADEON_GEM_DOMAIN_GTT)
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flags = DRM_BO_FLAG_MEM_TT; // need a can write gart check
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else
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return -EINVAL; // we can't write to system RAM
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} else {
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/* okay for a read domain - prefer wherever the object is now or close enough */
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if ((read_domains == 0) || (read_domains == RADEON_GEM_DOMAIN_CPU))
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return -EINVAL;
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/* simple case no choice in domains */
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if (read_domains == RADEON_GEM_DOMAIN_VRAM)
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flags = DRM_BO_FLAG_MEM_VRAM;
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else if (read_domains == RADEON_GEM_DOMAIN_GTT)
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flags = DRM_BO_FLAG_MEM_TT;
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else if ((obj_priv->bo->mem.mem_type == DRM_BO_MEM_VRAM) && (read_domains & RADEON_GEM_DOMAIN_VRAM))
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flags = DRM_BO_FLAG_MEM_VRAM;
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else if ((obj_priv->bo->mem.mem_type == DRM_BO_MEM_TT) && (read_domains & RADEON_GEM_DOMAIN_GTT))
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flags = DRM_BO_FLAG_MEM_TT;
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else if (read_domains & RADEON_GEM_DOMAIN_VRAM)
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flags = DRM_BO_FLAG_MEM_VRAM;
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else if (read_domains & RADEON_GEM_DOMAIN_GTT)
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flags = DRM_BO_FLAG_MEM_TT;
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}
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ret = drm_bo_do_validate(obj_priv->bo, flags, DRM_BO_MASK_MEM | DRM_BO_FLAG_CACHED,
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unfenced ? DRM_BO_HINT_DONT_FENCE : 0, 0);
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if (ret)
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return ret;
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if (flags_p)
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*flags_p = flags;
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return 0;
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}
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int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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@ -152,6 +204,7 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
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struct drm_gem_object *obj;
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struct drm_radeon_gem_object *obj_priv;
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int ret;
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/* for now if someone requests domain CPU - just make sure the buffer is finished with */
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/* just do a BO wait for now */
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@ -161,9 +214,7 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
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obj_priv = obj->driver_private;
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mutex_lock(&obj_priv->bo->mutex);
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ret = drm_bo_wait(obj_priv->bo, 0, 1, 0, 0);
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mutex_unlock(&obj_priv->bo->mutex);
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ret = radeon_gem_set_domain(obj, args->read_domains, args->write_domain, NULL, true);
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mutex_lock(&dev->struct_mutex);
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drm_gem_object_unreference(obj);
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@ -180,7 +231,41 @@ int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
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int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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return -ENOSYS;
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struct drm_radeon_gem_pwrite *args = data;
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struct drm_gem_object *obj;
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struct drm_radeon_gem_object *obj_priv;
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int ret;
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obj = drm_gem_object_lookup(dev, file_priv, args->handle);
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if (obj == NULL)
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return -EINVAL;
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obj_priv = obj->driver_private;
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/* check where the buffer is first - if not in VRAM
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fallback to userspace copying for now */
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mutex_lock(&obj_priv->bo->mutex);
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if (obj_priv->bo->mem.mem_type != DRM_BO_MEM_VRAM) {
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ret = -EINVAL;
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goto out_unlock;
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}
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DRM_ERROR("pwriting data->size %lld %llx\n", args->size, args->offset);
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ret = -EINVAL;
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#if 0
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/* so need to grab an IB, copy the data into it in a loop
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and send them to VRAM using HDB */
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while ((buf = radeon_host_data_blit(dev, cpp, w, dst_pitch_off, &buf_pitch,
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x, &y, (unsigned int*)&h, &hpass)) != 0) {
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radeon_host_data_blit_copy_pass(dev, cpp, buf, (uint8_t *)src,
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hpass, buf_pitch, src_pitch);
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src += hpass * src_pitch;
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}
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#endif
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out_unlock:
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mutex_unlock(&obj_priv->bo->mutex);
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return ret;
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}
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int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
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@ -215,7 +300,7 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
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obj_priv->bo->map_list.hash.key);
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up_write(¤t->mm->mmap_sem);
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DRM_DEBUG("got here %p\n", obj);
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DRM_DEBUG("got here %p %d\n", obj, obj_priv->bo->mem.mem_type);
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mutex_lock(&dev->struct_mutex);
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drm_gem_object_unreference(obj);
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mutex_unlock(&dev->struct_mutex);
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@ -246,8 +331,8 @@ int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
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/* validate into a pin with no fence */
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if (!(obj_priv->bo->type != drm_bo_type_kernel && !DRM_SUSER(DRM_CURPROC))) {
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ret = drm_bo_do_validate(obj_priv->bo, 0, DRM_BO_FLAG_NO_EVICT,
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DRM_BO_HINT_DONT_FENCE, 0);
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ret = drm_bo_do_validate(obj_priv->bo, 0, DRM_BO_FLAG_NO_EVICT,
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DRM_BO_HINT_DONT_FENCE, 0);
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} else
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ret = 0;
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@ -342,18 +427,6 @@ int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data,
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+ obj_priv->bo->offset + start);
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int dwords = (end - start + 3) / sizeof(u32);
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#if 0
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/* Indirect buffer data must be an even number of
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* dwords, so if we've been given an odd number we must
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* pad the data with a Type-2 CP packet.
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*/
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if (dwords & 1) {
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u32 *data = (u32 *)
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((char *)dev->agp_buffer_map->handle
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+ buf->offset + start);
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data[dwords++] = RADEON_CP_PACKET2;
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}
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#endif
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/* Fire off the indirect buffer */
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BEGIN_RING(3);
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@ -487,6 +560,7 @@ static int radeon_gart_init(struct drm_device *dev)
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/* setup a 32MB GART */
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dev_priv->gart_size = dev_priv->mm.gart_size;
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dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
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#if __OS_HAS_AGP
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@ -706,6 +780,9 @@ int radeon_gem_mm_init(struct drm_device *dev)
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int ret;
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u32 pg_offset;
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/* init TTM underneath */
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drm_bo_driver_init(dev);
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/* size the mappable VRAM memory for now */
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radeon_vram_setup(dev);
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@ -748,7 +825,6 @@ void radeon_gem_mm_fini(struct drm_device *dev)
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mutex_lock(&dev->struct_mutex);
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if (dev_priv->mm.ring_read.bo) {
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drm_bo_kunmap(&dev_priv->mm.ring_read.kmap);
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drm_bo_usage_deref_locked(&dev_priv->mm.ring_read.bo);
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@ -771,13 +847,13 @@ void radeon_gem_mm_fini(struct drm_device *dev)
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}
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if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1)) {
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DRM_DEBUG("delaying takedown of TTM memory\n");
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DRM_DEBUG("delaying takedown of VRAM memory\n");
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}
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mutex_unlock(&dev->struct_mutex);
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drm_bo_driver_finish(dev);
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dev_priv->mm_enabled = false;
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dev_priv->mm_enabled = false;
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}
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int radeon_gem_object_pin(struct drm_gem_object *obj,
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@ -899,7 +975,8 @@ static int radeon_gem_relocate(struct drm_device *dev, struct drm_file *file_pri
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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/* relocate the handle */
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int domains = reloc[2];
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uint32_t read_domains = reloc[2];
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uint32_t write_domain = reloc[3];
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struct drm_gem_object *obj;
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int flags = 0;
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int ret;
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@ -910,19 +987,11 @@ static int radeon_gem_relocate(struct drm_device *dev, struct drm_file *file_pri
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return false;
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obj_priv = obj->driver_private;
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if (domains == RADEON_GEM_DOMAIN_VRAM) {
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flags = DRM_BO_FLAG_MEM_VRAM;
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} else {
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flags = DRM_BO_FLAG_MEM_TT;
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}
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ret = drm_bo_do_validate(obj_priv->bo, flags, DRM_BO_MASK_MEM, 0, 0);
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if (ret)
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return ret;
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radeon_gem_set_domain(obj, read_domains, write_domain, &flags, false);
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if (flags == DRM_BO_FLAG_MEM_VRAM)
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*offset = obj_priv->bo->offset + dev_priv->fb_location;
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else
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else if (flags == DRM_BO_FLAG_MEM_TT)
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*offset = obj_priv->bo->offset + dev_priv->gart_vm_start;
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/* BAD BAD BAD - LINKED LIST THE OBJS and UNREF ONCE IB is SUBMITTED */
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@ -784,12 +784,9 @@ typedef struct drm_radeon_surface_free {
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#define DRM_RADEON_VBLANK_CRTC1 1
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#define DRM_RADEON_VBLANK_CRTC2 2
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#define RADEON_GEM_DOMAIN_CPU 0x1
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#define RADEON_GEM_DOMAIN_VRAM 0x2
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#define RADEON_GEM_DOMAIN_2D 0x4
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#define RADEON_GEM_DOMAIN_3D 0x8
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#define RADEON_GEM_DOMAIN_TEXTURE 0x10
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#define RADEON_GEM_DOMAIN_GPU 0x20 // for vertex buffers
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#define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain
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#define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed
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#define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain
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/* return to userspace start/size of gtt and vram apertures */
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struct drm_radeon_gem_info {
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