Merge branch 'master' into crestline
Nian Wu
commit
3886b7e629
|
|
@ -587,6 +587,7 @@
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|||
0x10de 0x01d7 NV_44 "Quadro NVS 110M / GeForce Go 7300"
|
||||
0x10de 0x01d8 NV_44 "GeForce Go 7400"
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||||
0x10de 0x01da NV_44 "Quadro NVS 110M"
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||||
0x10de 0x01dc NV_44 "Quadro FX 350M"
|
||||
0x10de 0x01df NV_44 "GeForce 7300 GS"
|
||||
0x10de 0x01f0 NV_17|NV_NFORCE2 "GeForce4 MX - nForce GPU"
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||||
0x10de 0x0200 NV_20 "GeForce3"
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||||
|
|
@ -600,6 +601,7 @@
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|||
0x10de 0x0221 NV_44 "GeForce 6200"
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||||
0x10de 0x0240 NV_44 "GeForce 6150"
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||||
0x10de 0x0242 NV_44 "GeForce 6100"
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||||
0x10de 0x0244 NV_44 "GeForce 6150 Go"
|
||||
0x10de 0x0250 NV_25 "GeForce4 Ti 4600"
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||||
0x10de 0x0251 NV_25 "GeForce4 Ti 4400"
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||||
0x10de 0x0252 NV_25 "GeForce4 Ti"
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||||
|
|
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|||
|
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@ -254,6 +254,12 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
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#define I915REG_INT_ENABLE_R 0x020a0
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#define I915REG_INSTPM 0x020c0
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#define I915REG_PIPEASTAT 0x70024
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#define I915REG_PIPEBSTAT 0x71024
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#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
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#define I915_VBLANK_CLEAR (1UL<<1)
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#define SRX_INDEX 0x3c4
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#define SRX_DATA 0x3c5
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#define SR01 1
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||||
|
|
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|||
|
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@ -214,9 +214,12 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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drm_device_t *dev = (drm_device_t *) arg;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u16 temp;
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u32 pipea_stats, pipeb_stats;
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pipea_stats = I915_READ(I915REG_PIPEASTAT);
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pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
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temp = I915_READ16(I915REG_INT_IDENTITY_R);
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temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG);
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#if 0
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@ -257,6 +260,12 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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if (dev_priv->swaps_pending > 0)
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drm_locked_tasklet(dev, i915_vblank_tasklet);
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I915_WRITE(I915REG_PIPEASTAT,
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pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
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I915_VBLANK_CLEAR);
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I915_WRITE(I915REG_PIPEBSTAT,
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pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
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I915_VBLANK_CLEAR);
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}
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return IRQ_HANDLED;
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|
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@ -93,6 +93,7 @@ drm_nouveau_mem_free_t;
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#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
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typedef struct drm_nouveau_getparam {
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unsigned int param;
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unsigned int dummy;
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uint64_t value;
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}
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drm_nouveau_getparam_t;
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|
|
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@ -34,7 +34,7 @@
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#define DRIVER_MAJOR 0
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#define DRIVER_MINOR 0
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#define DRIVER_PATCHLEVEL 2
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#define DRIVER_PATCHLEVEL 3
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#define NOUVEAU_FAMILY 0x0000FFFF
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#define NOUVEAU_FLAGS 0xFFFF0000
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|
|
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@ -368,12 +368,7 @@ static void nouveau_nv30_context_init(drm_device_t *dev,
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RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
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RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
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RAMFC_WR(SEMAPHORE, NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
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NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, grctx_inst); /* Misnomer. Really a ptr to the grctx */
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/*
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* TODO: We need to put this somewhere...
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*/
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/* INSTANCE_WR(dev_priv->ctx_table, init->channel, grctx_inst); */
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RAMFC_WR(DMA_SUBROUTINE, init->put_base);
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}
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||||
|
|
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|||
|
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@ -295,10 +295,10 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
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nstatus = NV_READ(0x00400104);
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nsource = NV_READ(0x00400108);
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DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
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DRM_ERROR("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
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instance = NV_READ(0x00400158);
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DRM_DEBUG("instance:0x%08x\n", instance);
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DRM_ERROR("instance:0x%08x\n", instance);
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address = NV_READ(0x400704);
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data = NV_READ(0x400708);
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||||
|
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@ -330,6 +330,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
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nouveau_nv10_context_switch(dev);
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||||
break;
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||||
case NV_20:
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||||
case NV_30:
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||||
nouveau_nv20_context_switch(dev);
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break;
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default:
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|
|
|
|||
|
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@ -96,8 +96,8 @@ int nouveau_firstopen(struct drm_device *dev)
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|||
/* FIXME: doesn't belong here, and have no idea what it's for.. */
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if (dev_priv->card_type >= NV_40)
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nv40_graph_init(dev);
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else if (dev_priv->card_type >= NV_30) {
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||||
}
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else if (dev_priv->card_type >= NV_30)
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nv30_graph_init(dev);
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else if (dev_priv->card_type >= NV_20)
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||||
nv20_graph_init(dev);
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else if (dev_priv->card_type >= NV_10)
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||||
|
|
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|||
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@ -8,10 +8,9 @@
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|||
#include "nouveau_drm.h"
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||||
/*
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* TODO: In the dump start seems to be 7654b0 while end is 76ac28.
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* This is obviously not the correct size.
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||||
*/
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||||
#define NV30_GRCTX_SIZE (22392)
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#define NV30_GRCTX_SIZE (23840)
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||||
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||||
/*TODO: deciper what each offset in the context represents. The below
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||||
* contexts are taken from dumps just after the 3D object is
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||||
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@ -21,7 +20,7 @@ static void nv30_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
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|||
{
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||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
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int i;
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||||
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INSTANCE_WR(ctx, 0x28/4, 0x10000000);
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INSTANCE_WR(ctx, 0x40c/4, 0x00000101);
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INSTANCE_WR(ctx, 0x420/4, 0x00000111);
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||||
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@ -101,8 +100,7 @@ static void nv30_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
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|||
}
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||||
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||||
int
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||||
nv30_graph_context_create(drm_device_t *dev, int channel)
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||||
int nv30_graph_context_create(drm_device_t *dev, int channel)
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||||
{
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drm_nouveau_private_t *dev_priv =
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(drm_nouveau_private_t *)dev->dev_private;
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||||
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@ -128,97 +126,14 @@ nv30_graph_context_create(drm_device_t *dev, int channel)
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|||
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/* Initialise default context values */
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||||
ctx_init(dev, chan->ramin_grctx);
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||||
|
||||
INSTANCE_WR(chan->ramin_grctx, 10, channel << 24); /* CTX_USER */
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INSTANCE_WR(dev_priv->ctx_table, channel, nouveau_chip_instance_get(dev, chan->ramin_grctx));
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||||
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return 0;
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||||
}
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||||
#if 0
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||||
/* Save current context (from PGRAPH) into the channel's context
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||||
*XXX: fails sometimes, not sure why..
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||||
*/
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||||
void
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nv40_graph_context_save_current(drm_device_t *dev)
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||||
{
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drm_nouveau_private_t *dev_priv =
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(drm_nouveau_private_t *)dev->dev_private;
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uint32_t instance;
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int i;
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||||
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NV_WRITE(NV_PGRAPH_FIFO, 0);
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instance = NV_READ(0x40032C) & 0xFFFFF;
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if (!instance) {
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NV_WRITE(NV_PGRAPH_FIFO, 1);
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return;
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}
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NV_WRITE(0x400784, instance);
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NV_WRITE(0x400310, NV_READ(0x400310) | 0x20);
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NV_WRITE(0x400304, 1);
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/* just in case, we don't want to spin in-kernel forever */
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for (i=0; i<1000; i++) {
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if (NV_READ(0x40030C) == 0)
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||||
break;
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||||
}
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if (i==1000) {
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DRM_ERROR("failed to save current grctx to ramin\n");
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DRM_ERROR("instance = 0x%08x\n", NV_READ(0x40032C));
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DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
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NV_WRITE(NV_PGRAPH_FIFO, 1);
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return;
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}
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||||
NV_WRITE(NV_PGRAPH_FIFO, 1);
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}
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/* Restore the context for a specific channel into PGRAPH
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* XXX: fails sometimes.. not sure why
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||||
*/
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||||
void
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nv40_graph_context_restore(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv =
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(drm_nouveau_private_t *)dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[channel];
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uint32_t instance;
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int i;
|
||||
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instance = nouveau_chip_instance_get(dev, chan->ramin_grctx);
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||||
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NV_WRITE(NV_PGRAPH_FIFO, 0);
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NV_WRITE(0x400784, instance);
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NV_WRITE(0x400310, NV_READ(0x400310) | 0x40);
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NV_WRITE(0x400304, 1);
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/* just in case, we don't want to spin in-kernel forever */
|
||||
for (i=0; i<1000; i++) {
|
||||
if (NV_READ(0x40030C) == 0)
|
||||
break;
|
||||
}
|
||||
if (i==1000) {
|
||||
DRM_ERROR("failed to restore grctx for ch%d to PGRAPH\n",
|
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channel);
|
||||
DRM_ERROR("instance = 0x%08x\n", instance);
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DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
|
||||
NV_WRITE(NV_PGRAPH_FIFO, 1);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/* 0x40032C, no idea of it's exact function. Could simply be a
|
||||
* record of the currently active PGRAPH context. It's currently
|
||||
* unknown as to what bit 24 does. The nv ddx has it set, so we will
|
||||
* set it here too.
|
||||
*/
|
||||
NV_WRITE(0x40032C, instance | 0x01000000);
|
||||
/* 0x32E0 records the instance address of the active FIFO's PGRAPH
|
||||
* context. If at any time this doesn't match 0x40032C, you will
|
||||
* recieve PGRAPH_INTR_CONTEXT_SWITCH
|
||||
*/
|
||||
NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, instance);
|
||||
NV_WRITE(NV_PGRAPH_FIFO, 1);
|
||||
}
|
||||
#endif
|
||||
int
|
||||
nv30_graph_init(drm_device_t *dev)
|
||||
int nv30_graph_init(drm_device_t *dev)
|
||||
{
|
||||
drm_nouveau_private_t *dev_priv =
|
||||
(drm_nouveau_private_t *)dev->dev_private;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#define NV40_GRCTX_SIZE (175*1024)
|
||||
#define NV43_GRCTX_SIZE (70*1024)
|
||||
#define NV4A_GRCTX_SIZE (64*1024)
|
||||
#define NV4C_GRCTX_SIZE (25*1024)
|
||||
#define NV4E_GRCTX_SIZE (25*1024)
|
||||
|
||||
/*TODO: deciper what each offset in the context represents. The below
|
||||
|
|
@ -389,6 +390,113 @@ static void nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
|
|||
INSTANCE_WR(ctx, i/4, 0x3f800000);
|
||||
}
|
||||
|
||||
|
||||
static void nv4c_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
|
||||
{
|
||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
|
||||
int i;
|
||||
|
||||
INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx));
|
||||
INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);
|
||||
INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);
|
||||
INSTANCE_WR(ctx, 0x00030/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);
|
||||
INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);
|
||||
INSTANCE_WR(ctx, 0x00128/4, 0x02008821);
|
||||
INSTANCE_WR(ctx, 0x00158/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x0015c/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x00160/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x00164/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x00168/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x0016c/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x00170/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x00174/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x00178/4, 0x00000040);
|
||||
INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);
|
||||
INSTANCE_WR(ctx, 0x00180/4, 0x00000040);
|
||||
INSTANCE_WR(ctx, 0x00188/4, 0x00000040);
|
||||
INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);
|
||||
INSTANCE_WR(ctx, 0x00340/4, 0x00040000);
|
||||
INSTANCE_WR(ctx, 0x00350/4, 0x55555555);
|
||||
INSTANCE_WR(ctx, 0x00354/4, 0x55555555);
|
||||
INSTANCE_WR(ctx, 0x00358/4, 0x55555555);
|
||||
INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);
|
||||
INSTANCE_WR(ctx, 0x00388/4, 0x00000008);
|
||||
INSTANCE_WR(ctx, 0x0039c/4, 0x00001010);
|
||||
INSTANCE_WR(ctx, 0x003d0/4, 0x00000111);
|
||||
INSTANCE_WR(ctx, 0x003d4/4, 0x00080060);
|
||||
INSTANCE_WR(ctx, 0x003f0/4, 0x00000080);
|
||||
INSTANCE_WR(ctx, 0x003f4/4, 0xffff0000);
|
||||
INSTANCE_WR(ctx, 0x003f8/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x0040c/4, 0x46400000);
|
||||
INSTANCE_WR(ctx, 0x0041c/4, 0xffff0000);
|
||||
INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);
|
||||
INSTANCE_WR(ctx, 0x0042c/4, 0x0fff0000);
|
||||
INSTANCE_WR(ctx, 0x00434/4, 0x00011100);
|
||||
for (i=0x00450; i<0x0048c; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x07ff0000);
|
||||
INSTANCE_WR(ctx, 0x00498/4, 0x4b7fffff);
|
||||
INSTANCE_WR(ctx, 0x004c0/4, 0x30201000);
|
||||
INSTANCE_WR(ctx, 0x004c4/4, 0x70605040);
|
||||
INSTANCE_WR(ctx, 0x004c8/4, 0xb8a89888);
|
||||
INSTANCE_WR(ctx, 0x004cc/4, 0xf8e8d8c8);
|
||||
INSTANCE_WR(ctx, 0x004e0/4, 0x40100000);
|
||||
INSTANCE_WR(ctx, 0x004fc/4, 0x0000ffff);
|
||||
INSTANCE_WR(ctx, 0x00530/4, 0x435185d6);
|
||||
INSTANCE_WR(ctx, 0x00534/4, 0x2155b699);
|
||||
INSTANCE_WR(ctx, 0x00538/4, 0xfedcba98);
|
||||
INSTANCE_WR(ctx, 0x0053c/4, 0x00000098);
|
||||
INSTANCE_WR(ctx, 0x0054c/4, 0xffffffff);
|
||||
INSTANCE_WR(ctx, 0x00550/4, 0x00ff7000);
|
||||
INSTANCE_WR(ctx, 0x00554/4, 0x0000ffff);
|
||||
INSTANCE_WR(ctx, 0x00564/4, 0x00ff0000);
|
||||
INSTANCE_WR(ctx, 0x0059c/4, 0x00ffff00);
|
||||
for (i=0x005e0; i<=0x0061c; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x00018488);
|
||||
for (i=0x00620; i<=0x0065c; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x00028202);
|
||||
for (i=0x006a0; i<=0x006dc; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x0000aae4);
|
||||
for (i=0x006e0; i<=0x0071c; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x01012000);
|
||||
for (i=0x00720; i<=0x0075c; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x00080008);
|
||||
for (i=0x007a0; i<=0x007dc; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x00100008);
|
||||
for (i=0x00830; i<=0x0083c; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x0001bc80);
|
||||
for (i=0x00840; i<=0x0084c; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x00000202);
|
||||
for (i=0x00860; i<=0x0086c; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x00000008);
|
||||
for (i=0x00880; i<=0x0088c; i+=4)
|
||||
INSTANCE_WR(ctx, i/4, 0x00080008);
|
||||
INSTANCE_WR(ctx, 0x008a0/4, 0x00000002);
|
||||
INSTANCE_WR(ctx, 0x008d4/4, 0x00000020);
|
||||
INSTANCE_WR(ctx, 0x008d8/4, 0x030c30c3);
|
||||
INSTANCE_WR(ctx, 0x008dc/4, 0x00011001);
|
||||
INSTANCE_WR(ctx, 0x008e8/4, 0x3e020200);
|
||||
INSTANCE_WR(ctx, 0x008ec/4, 0x00ffffff);
|
||||
INSTANCE_WR(ctx, 0x008f0/4, 0x0c103f00);
|
||||
INSTANCE_WR(ctx, 0x008fc/4, 0x00040000);
|
||||
INSTANCE_WR(ctx, 0x00934/4, 0x00008100);
|
||||
INSTANCE_WR(ctx, 0x009c0/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x00a04/4, 0x00001001);
|
||||
INSTANCE_WR(ctx, 0x00a0c/4, 0x00000003);
|
||||
INSTANCE_WR(ctx, 0x00a10/4, 0x00888001);
|
||||
INSTANCE_WR(ctx, 0x00a74/4, 0x00000005);
|
||||
INSTANCE_WR(ctx, 0x00a80/4, 0x0000ffff);
|
||||
INSTANCE_WR(ctx, 0x00a9c/4, 0x00005555);
|
||||
INSTANCE_WR(ctx, 0x00aa0/4, 0x00000001);
|
||||
INSTANCE_WR(ctx, 0x00ad8/4, 0x00000001);
|
||||
for (i=0x016a0; i<0x01718; i+=8)
|
||||
INSTANCE_WR(ctx, i/4, 0x3f800000);
|
||||
for (i=0x03460; i<0x05650; i+=24)
|
||||
INSTANCE_WR(ctx, i/4, 0x00000001);
|
||||
for (i=0x05660; i<0x05a50; i+=16)
|
||||
INSTANCE_WR(ctx, i/4, 0x3f800000);
|
||||
}
|
||||
|
||||
static void nv4e_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
|
||||
{
|
||||
drm_nouveau_private_t *dev_priv = dev->dev_private;
|
||||
|
|
@ -519,6 +627,10 @@ nv40_graph_context_create(drm_device_t *dev, int channel)
|
|||
ctx_size = NV4A_GRCTX_SIZE;
|
||||
ctx_init = nv4a_graph_context_init;
|
||||
break;
|
||||
case 0x4c:
|
||||
ctx_size = NV4C_GRCTX_SIZE;
|
||||
ctx_init = nv4c_graph_context_init;
|
||||
break;
|
||||
case 0x4e:
|
||||
ctx_size = NV4E_GRCTX_SIZE;
|
||||
ctx_init = nv4e_graph_context_init;
|
||||
|
|
|
|||
Loading…
Reference in New Issue