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radeon: sync radeon_drm.h with the kernel 

the CIK tile mode definitions are moved out,
userspace doesn't use them

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
main
Marek Olšák 2016-08-19 16:07:50 +02:00
parent 4462303700
commit 39fff59962
2 changed files with 50 additions and 9 deletions
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51
include/drm/radeon_drm.h
View File

@ -35,6 +35,10 @@
#include "drm.h" #include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* WARNING: If you change any of these defines, make sure to change the /* WARNING: If you change any of these defines, make sure to change the
* defines in the X server file (radeon_sarea.h) * defines in the X server file (radeon_sarea.h)
*/ */
@ -511,6 +515,7 @@ typedef struct {
#define DRM_RADEON_GEM_BUSY 0x2a #define DRM_RADEON_GEM_BUSY 0x2a
#define DRM_RADEON_GEM_VA 0x2b #define DRM_RADEON_GEM_VA 0x2b
#define DRM_RADEON_GEM_OP 0x2c #define DRM_RADEON_GEM_OP 0x2c
#define DRM_RADEON_GEM_USERPTR 0x2d
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
@ -554,6 +559,7 @@ typedef struct {
#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
#define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
typedef struct drm_radeon_init { typedef struct drm_radeon_init {
enum { enum {
@ -796,7 +802,13 @@ struct drm_radeon_gem_info {
uint64_t vram_visible; uint64_t vram_visible;
}; };
#define RADEON_GEM_NO_BACKING_STORE 1 #define RADEON_GEM_NO_BACKING_STORE (1 << 0)
#define RADEON_GEM_GTT_UC (1 << 1)
#define RADEON_GEM_GTT_WC (1 << 2)
/* BO is expected to be accessed by the CPU */
#define RADEON_GEM_CPU_ACCESS (1 << 3)
/* CPU access is not expected to work for this BO */
#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
struct drm_radeon_gem_create { struct drm_radeon_gem_create {
uint64_t size; uint64_t size;
@ -806,6 +818,23 @@ struct drm_radeon_gem_create {
uint32_t flags; uint32_t flags;
}; };
/*
* This is not a reliable API and you should expect it to fail for any
* number of reasons and have fallback path that do not use userptr to
* perform any operation.
*/
#define RADEON_GEM_USERPTR_READONLY (1 << 0)
#define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
#define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
#define RADEON_GEM_USERPTR_REGISTER (1 << 3)
struct drm_radeon_gem_userptr {
uint64_t addr;
uint64_t size;
uint32_t flags;
uint32_t handle;
};
#define RADEON_TILING_MACRO 0x1 #define RADEON_TILING_MACRO 0x1
#define RADEON_TILING_MICRO 0x2 #define RADEON_TILING_MICRO 0x2
#define RADEON_TILING_SWAP_16BIT 0x4 #define RADEON_TILING_SWAP_16BIT 0x4
@ -943,6 +972,7 @@ struct drm_radeon_cs_chunk {
}; };
/* drm_radeon_cs_reloc.flags */ /* drm_radeon_cs_reloc.flags */
#define RADEON_RELOC_PRIO_MASK (0xf << 0)
struct drm_radeon_cs_reloc { struct drm_radeon_cs_reloc {
uint32_t handle; uint32_t handle;
@ -1008,7 +1038,13 @@ struct drm_radeon_cs {
#define RADEON_INFO_NUM_BYTES_MOVED 0x1d #define RADEON_INFO_NUM_BYTES_MOVED 0x1d
#define RADEON_INFO_VRAM_USAGE 0x1e #define RADEON_INFO_VRAM_USAGE 0x1e
#define RADEON_INFO_GTT_USAGE 0x1f #define RADEON_INFO_GTT_USAGE 0x1f
#define RADEON_INFO_ACTIVE_CU_COUNT 0x20
#define RADEON_INFO_CURRENT_GPU_TEMP 0x21
#define RADEON_INFO_CURRENT_GPU_SCLK 0x22
#define RADEON_INFO_CURRENT_GPU_MCLK 0x23
#define RADEON_INFO_READ_REG 0x24
#define RADEON_INFO_VA_UNMAP_WORKING 0x25
#define RADEON_INFO_GPU_RESET_COUNTER 0x26
struct drm_radeon_info { struct drm_radeon_info {
uint32_t request; uint32_t request;
@ -1034,13 +1070,10 @@ struct drm_radeon_info {
#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
#define CIK_TILE_MODE_COLOR_2D 14
#define CIK_TILE_MODE_COLOR_2D_SCANOUT 10
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64 0
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128 1
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256 2
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512 3
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4
#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
#if defined(__cplusplus)
}
#endif
#endif #endif

8
radeon/radeon_surface.c
View File

@ -42,6 +42,14 @@
#include "radeon_drm.h" #include "radeon_drm.h"
#include "radeon_surface.h" #include "radeon_surface.h"
#define CIK_TILE_MODE_COLOR_2D 14
#define CIK_TILE_MODE_COLOR_2D_SCANOUT 10
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64 0
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128 1
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256 2
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512 3
#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4
#define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1)) #define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1))
#define MAX2(A, B) ((A) > (B) ? (A) : (B)) #define MAX2(A, B) ((A) > (B) ? (A) : (B))
#define MIN2(A, B) ((A) < (B) ? (A) : (B)) #define MIN2(A, B) ((A) < (B) ? (A) : (B))