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nv50: some cleanups + small changes

main
Ben Skeggs 2008-01-07 16:52:47 +11:00
parent cd19dcef4f
commit 3d3d509dca
2 changed files with 57 additions and 55 deletions
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90
shared-core/nv50_fifo.c
View File

@ -28,9 +28,10 @@
#include "drm.h" #include "drm.h"
#include "nouveau_drv.h" #include "nouveau_drv.h"
typedef struct { struct nv50_fifo_priv {
struct nouveau_gpuobj_ref *thingo; struct nouveau_gpuobj_ref *thingo[2];
} nv50_fifo_priv; int cur_thingo;
};
#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
@ -38,23 +39,23 @@ static void
nv50_fifo_init_thingo(struct drm_device *dev) nv50_fifo_init_thingo(struct drm_device *dev)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
struct nouveau_gpuobj_ref *thingo = priv->thingo; struct nouveau_gpuobj_ref *cur;
int i, fi=2; int i, nr;
DRM_DEBUG("\n"); DRM_DEBUG("\n");
INSTANCE_WR(thingo->gpuobj, 0, 0x7e); cur = priv->thingo[priv->cur_thingo];
INSTANCE_WR(thingo->gpuobj, 1, 0x7e); priv->cur_thingo = !priv->cur_thingo;
for (i = 1; i < 127; i++, fi) {
if (dev_priv->fifos[i]) {
INSTANCE_WR(thingo->gpuobj, fi, i);
fi++;
}
}
NV_WRITE(0x32f4, thingo->instance >> 12); /* We never schedule channel 0 or 127 */
NV_WRITE(0x32ec, fi); for (i = 1, nr = 0; i < 127; i++) {
if (dev_priv->fifos[i]) {
INSTANCE_WR(cur->gpuobj, nr++, i);
}
}
NV_WRITE(0x32f4, cur->instance >> 12);
NV_WRITE(0x32ec, nr);
NV_WRITE(0x2500, 0x101); NV_WRITE(0x2500, 0x101);
} }
@ -98,14 +99,12 @@ static void
nv50_fifo_init_reset(struct drm_device *dev) nv50_fifo_init_reset(struct drm_device *dev)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t pmc_e; uint32_t pmc_e = NV_PMC_ENABLE_PFIFO;
DRM_DEBUG("\n"); DRM_DEBUG("\n");
pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PFIFO); NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e);
pmc_e = NV_READ(NV03_PMC_ENABLE);
NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO);
} }
static void static void
@ -141,7 +140,7 @@ nv50_fifo_init_regs__nv(struct drm_device *dev)
NV_WRITE(0x250c, 0x6f3cfc34); NV_WRITE(0x250c, 0x6f3cfc34);
} }
static int static void
nv50_fifo_init_regs(struct drm_device *dev) nv50_fifo_init_regs(struct drm_device *dev)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
@ -158,15 +157,13 @@ nv50_fifo_init_regs(struct drm_device *dev)
/* Enable dummy channels setup by nv50_instmem.c */ /* Enable dummy channels setup by nv50_instmem.c */
nv50_fifo_channel_enable(dev, 0, 1); nv50_fifo_channel_enable(dev, 0, 1);
nv50_fifo_channel_enable(dev, 127, 1); nv50_fifo_channel_enable(dev, 127, 1);
return 0;
} }
int int
nv50_fifo_init(struct drm_device *dev) nv50_fifo_init(struct drm_device *dev)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
nv50_fifo_priv *priv; struct nv50_fifo_priv *priv;
int ret; int ret;
DRM_DEBUG("\n"); DRM_DEBUG("\n");
@ -179,18 +176,23 @@ nv50_fifo_init(struct drm_device *dev)
nv50_fifo_init_reset(dev); nv50_fifo_init_reset(dev);
nv50_fifo_init_intr(dev); nv50_fifo_init_intr(dev);
if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000, ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
NVOBJ_FLAG_ZERO_ALLOC, NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[0]);
&priv->thingo))) { if (ret) {
DRM_ERROR("error creating thingo: %d\n", ret); DRM_ERROR("error creating thingo0: %d\n", ret);
return ret;
}
ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[1]);
if (ret) {
DRM_ERROR("error creating thingo1: %d\n", ret);
return ret; return ret;
} }
nv50_fifo_init_context_table(dev); nv50_fifo_init_context_table(dev);
nv50_fifo_init_regs__nv(dev); nv50_fifo_init_regs__nv(dev);
if ((ret = nv50_fifo_init_regs(dev))) nv50_fifo_init_regs(dev);
return ret;
return 0; return 0;
} }
@ -199,14 +201,15 @@ void
nv50_fifo_takedown(struct drm_device *dev) nv50_fifo_takedown(struct drm_device *dev)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
DRM_DEBUG("\n"); DRM_DEBUG("\n");
if (!priv) if (!priv)
return; return;
nouveau_gpuobj_ref_del(dev, &priv->thingo); nouveau_gpuobj_ref_del(dev, &priv->thingo[0]);
nouveau_gpuobj_ref_del(dev, &priv->thingo[1]);
dev_priv->Engine.fifo.priv = NULL; dev_priv->Engine.fifo.priv = NULL;
drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
@ -234,18 +237,18 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
if (IS_G80) { if (IS_G80) {
uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start; uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start;
if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, vram_offset,
vram_offset, 0x100, 0x100, NVOBJ_FLAG_ZERO_ALLOC |
NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &ramfc,
NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
&ramfc, &chan->ramfc))) if (ret)
return ret; return ret;
} else { } else {
if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256,
256,
NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_ALLOC |
NVOBJ_FLAG_ZERO_FREE, NVOBJ_FLAG_ZERO_FREE,
&chan->ramfc))) &chan->ramfc);
if (ret)
return ret; return ret;
ramfc = chan->ramfc->gpuobj; ramfc = chan->ramfc->gpuobj;
} }
@ -272,7 +275,8 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12);
} }
if ((ret = nv50_fifo_channel_enable(dev, chan->id, 0))) { ret = nv50_fifo_channel_enable(dev, chan->id, 0);
if (ret) {
DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret); DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret);
nouveau_gpuobj_ref_del(dev, &chan->ramfc); nouveau_gpuobj_ref_del(dev, &chan->ramfc);
return ret; return ret;

18
shared-core/nv50_graph.c
View File

@ -34,14 +34,12 @@ static void
nv50_graph_init_reset(struct drm_device *dev) nv50_graph_init_reset(struct drm_device *dev)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t pmc_e; uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
DRM_DEBUG("\n"); DRM_DEBUG("\n");
pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PGRAPH); NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e);
pmc_e = NV_READ(NV03_PMC_ENABLE);
NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PGRAPH);
} }
static void static void
@ -253,11 +251,10 @@ nv50_graph_create_context(struct nouveau_channel *chan)
DRM_DEBUG("ch%d\n", chan->id); DRM_DEBUG("ch%d\n", chan->id);
if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, grctx_size, 0x1000,
grctx_size, 0x1000,
NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_ALLOC |
NVOBJ_FLAG_ZERO_FREE, NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
&chan->ramin_grctx))) if (ret)
return ret; return ret;
hdr = IS_G80 ? 0x200 : 0x20; hdr = IS_G80 ? 0x200 : 0x20;
@ -269,7 +266,8 @@ nv50_graph_create_context(struct nouveau_channel *chan)
INSTANCE_WR(ramin, (hdr + 0x10)/4, 0); INSTANCE_WR(ramin, (hdr + 0x10)/4, 0);
INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000); INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000);
if ((ret = engine->graph.load_context(chan))) { ret = engine->graph.load_context(chan);
if (ret) {
DRM_ERROR("Error hacking up initial context: %d\n", ret); DRM_ERROR("Error hacking up initial context: %d\n", ret);
return ret; return ret;
} }