nv50: some cleanups + small changes
Ben Skeggs
parent
cd19dcef4f
commit
3d3d509dca
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@ -28,9 +28,10 @@
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#include "drm.h"
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#include "nouveau_drv.h"
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typedef struct {
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struct nouveau_gpuobj_ref *thingo;
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} nv50_fifo_priv;
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struct nv50_fifo_priv {
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struct nouveau_gpuobj_ref *thingo[2];
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int cur_thingo;
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};
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#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
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@ -38,23 +39,23 @@ static void
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nv50_fifo_init_thingo(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
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struct nouveau_gpuobj_ref *thingo = priv->thingo;
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int i, fi=2;
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struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
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struct nouveau_gpuobj_ref *cur;
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int i, nr;
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DRM_DEBUG("\n");
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INSTANCE_WR(thingo->gpuobj, 0, 0x7e);
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INSTANCE_WR(thingo->gpuobj, 1, 0x7e);
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for (i = 1; i < 127; i++, fi) {
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if (dev_priv->fifos[i]) {
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INSTANCE_WR(thingo->gpuobj, fi, i);
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fi++;
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}
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}
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cur = priv->thingo[priv->cur_thingo];
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priv->cur_thingo = !priv->cur_thingo;
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NV_WRITE(0x32f4, thingo->instance >> 12);
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NV_WRITE(0x32ec, fi);
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/* We never schedule channel 0 or 127 */
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for (i = 1, nr = 0; i < 127; i++) {
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if (dev_priv->fifos[i]) {
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INSTANCE_WR(cur->gpuobj, nr++, i);
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}
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}
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NV_WRITE(0x32f4, cur->instance >> 12);
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NV_WRITE(0x32ec, nr);
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NV_WRITE(0x2500, 0x101);
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}
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@ -98,14 +99,12 @@ static void
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nv50_fifo_init_reset(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t pmc_e;
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uint32_t pmc_e = NV_PMC_ENABLE_PFIFO;
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DRM_DEBUG("\n");
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pmc_e = NV_READ(NV03_PMC_ENABLE);
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NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PFIFO);
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pmc_e = NV_READ(NV03_PMC_ENABLE);
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NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO);
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NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
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NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e);
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}
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static void
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@ -141,7 +140,7 @@ nv50_fifo_init_regs__nv(struct drm_device *dev)
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NV_WRITE(0x250c, 0x6f3cfc34);
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}
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static int
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static void
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nv50_fifo_init_regs(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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@ -158,15 +157,13 @@ nv50_fifo_init_regs(struct drm_device *dev)
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/* Enable dummy channels setup by nv50_instmem.c */
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nv50_fifo_channel_enable(dev, 0, 1);
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nv50_fifo_channel_enable(dev, 127, 1);
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return 0;
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}
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int
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nv50_fifo_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nv50_fifo_priv *priv;
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struct nv50_fifo_priv *priv;
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int ret;
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DRM_DEBUG("\n");
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@ -179,18 +176,23 @@ nv50_fifo_init(struct drm_device *dev)
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nv50_fifo_init_reset(dev);
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nv50_fifo_init_intr(dev);
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if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC,
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&priv->thingo))) {
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DRM_ERROR("error creating thingo: %d\n", ret);
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ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[0]);
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if (ret) {
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DRM_ERROR("error creating thingo0: %d\n", ret);
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return ret;
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}
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ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[1]);
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if (ret) {
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DRM_ERROR("error creating thingo1: %d\n", ret);
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return ret;
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}
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nv50_fifo_init_context_table(dev);
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nv50_fifo_init_regs__nv(dev);
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if ((ret = nv50_fifo_init_regs(dev)))
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return ret;
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nv50_fifo_init_regs(dev);
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return 0;
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}
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@ -199,14 +201,15 @@ void
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nv50_fifo_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
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struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
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DRM_DEBUG("\n");
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if (!priv)
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return;
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nouveau_gpuobj_ref_del(dev, &priv->thingo);
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nouveau_gpuobj_ref_del(dev, &priv->thingo[0]);
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nouveau_gpuobj_ref_del(dev, &priv->thingo[1]);
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dev_priv->Engine.fifo.priv = NULL;
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drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
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@ -234,18 +237,18 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
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if (IS_G80) {
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uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
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uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start;
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if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset,
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vram_offset, 0x100,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE,
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&ramfc, &chan->ramfc)))
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ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, vram_offset,
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0x100, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &ramfc,
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&chan->ramfc);
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if (ret)
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return ret;
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} else {
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if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100,
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256,
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE,
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&chan->ramfc)))
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&chan->ramfc);
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if (ret)
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return ret;
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ramfc = chan->ramfc->gpuobj;
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}
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@ -272,7 +275,8 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
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INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12);
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}
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if ((ret = nv50_fifo_channel_enable(dev, chan->id, 0))) {
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ret = nv50_fifo_channel_enable(dev, chan->id, 0);
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if (ret) {
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DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret);
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nouveau_gpuobj_ref_del(dev, &chan->ramfc);
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return ret;
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@ -34,14 +34,12 @@ static void
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nv50_graph_init_reset(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t pmc_e;
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uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
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DRM_DEBUG("\n");
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pmc_e = NV_READ(NV03_PMC_ENABLE);
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NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PGRAPH);
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pmc_e = NV_READ(NV03_PMC_ENABLE);
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NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PGRAPH);
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NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
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NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e);
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}
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static void
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@ -253,11 +251,10 @@ nv50_graph_create_context(struct nouveau_channel *chan)
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DRM_DEBUG("ch%d\n", chan->id);
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if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0,
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grctx_size, 0x1000,
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, grctx_size, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE,
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&chan->ramin_grctx)))
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NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
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if (ret)
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return ret;
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hdr = IS_G80 ? 0x200 : 0x20;
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@ -269,7 +266,8 @@ nv50_graph_create_context(struct nouveau_channel *chan)
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INSTANCE_WR(ramin, (hdr + 0x10)/4, 0);
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INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000);
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if ((ret = engine->graph.load_context(chan))) {
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ret = engine->graph.load_context(chan);
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if (ret) {
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DRM_ERROR("Error hacking up initial context: %d\n", ret);
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return ret;
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}
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