amdgpu: sync amdgpu_drm.h with kernel 4.11-rc2
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>main
Marek Olšák
parent
a07ae97c75
commit
3dc002df3e
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@ -50,6 +50,7 @@ extern "C" {
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#define DRM_AMDGPU_WAIT_CS 0x09
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#define DRM_AMDGPU_GEM_OP 0x10
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#define DRM_AMDGPU_GEM_USERPTR 0x11
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#define DRM_AMDGPU_WAIT_FENCES 0x12
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#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
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#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
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@ -63,6 +64,7 @@ extern "C" {
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#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
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#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
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#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
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#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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@ -79,22 +81,26 @@ extern "C" {
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#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
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/* Flag that the memory should be in VRAM and cleared */
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#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
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/* Flag that create shadow bo(GTT) while allocating vram bo */
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#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
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/* Flag that allocating the BO should use linear VRAM */
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#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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uint64_t bo_size;
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__u64 bo_size;
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/** physical start_addr alignment in bytes for some HW requirements */
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uint64_t alignment;
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__u64 alignment;
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/** the requested memory domains */
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uint64_t domains;
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__u64 domains;
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/** allocation flags */
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uint64_t domain_flags;
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__u64 domain_flags;
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};
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struct drm_amdgpu_gem_create_out {
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/** returned GEM object handle */
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uint32_t handle;
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uint32_t _pad;
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__u32 handle;
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__u32 _pad;
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};
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union drm_amdgpu_gem_create {
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@ -111,28 +117,28 @@ union drm_amdgpu_gem_create {
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struct drm_amdgpu_bo_list_in {
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/** Type of operation */
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uint32_t operation;
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__u32 operation;
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/** Handle of list or 0 if we want to create one */
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uint32_t list_handle;
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__u32 list_handle;
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/** Number of BOs in list */
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uint32_t bo_number;
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__u32 bo_number;
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/** Size of each element describing BO */
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uint32_t bo_info_size;
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__u32 bo_info_size;
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/** Pointer to array describing BOs */
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uint64_t bo_info_ptr;
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__u64 bo_info_ptr;
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};
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struct drm_amdgpu_bo_list_entry {
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/** Handle of BO */
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uint32_t bo_handle;
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__u32 bo_handle;
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/** New (if specified) BO priority to be used during migration */
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uint32_t bo_priority;
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__u32 bo_priority;
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};
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struct drm_amdgpu_bo_list_out {
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/** Handle of resource list */
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uint32_t list_handle;
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uint32_t _pad;
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__u32 list_handle;
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__u32 _pad;
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};
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union drm_amdgpu_bo_list {
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@ -156,26 +162,26 @@ union drm_amdgpu_bo_list {
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struct drm_amdgpu_ctx_in {
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/** AMDGPU_CTX_OP_* */
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uint32_t op;
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__u32 op;
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/** For future use, no flags defined so far */
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uint32_t flags;
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uint32_t ctx_id;
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uint32_t _pad;
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__u32 flags;
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__u32 ctx_id;
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__u32 _pad;
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};
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union drm_amdgpu_ctx_out {
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struct {
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uint32_t ctx_id;
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uint32_t _pad;
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__u32 ctx_id;
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__u32 _pad;
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} alloc;
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struct {
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/** For future use, no flags defined so far */
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uint64_t flags;
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__u64 flags;
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/** Number of resets caused by this context so far. */
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uint32_t hangs;
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__u32 hangs;
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/** Reset status since the last call of the ioctl. */
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uint32_t reset_status;
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__u32 reset_status;
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} state;
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};
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@ -195,12 +201,12 @@ union drm_amdgpu_ctx {
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#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
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struct drm_amdgpu_gem_userptr {
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uint64_t addr;
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uint64_t size;
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__u64 addr;
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__u64 size;
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/* AMDGPU_GEM_USERPTR_* */
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uint32_t flags;
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__u32 flags;
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/* Resulting GEM handle */
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uint32_t handle;
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__u32 handle;
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};
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/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
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@ -232,28 +238,28 @@ struct drm_amdgpu_gem_userptr {
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/** The same structure is shared for input/output */
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struct drm_amdgpu_gem_metadata {
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/** GEM Object handle */
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uint32_t handle;
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__u32 handle;
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/** Do we want get or set metadata */
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uint32_t op;
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__u32 op;
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struct {
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/** For future use, no flags defined so far */
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uint64_t flags;
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__u64 flags;
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/** family specific tiling info */
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uint64_t tiling_info;
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uint32_t data_size_bytes;
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uint32_t data[64];
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__u64 tiling_info;
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__u32 data_size_bytes;
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__u32 data[64];
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} data;
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};
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struct drm_amdgpu_gem_mmap_in {
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/** the GEM object handle */
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uint32_t handle;
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uint32_t _pad;
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__u32 handle;
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__u32 _pad;
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};
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struct drm_amdgpu_gem_mmap_out {
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/** mmap offset from the vma offset manager */
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uint64_t addr_ptr;
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__u64 addr_ptr;
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};
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union drm_amdgpu_gem_mmap {
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@ -263,18 +269,18 @@ union drm_amdgpu_gem_mmap {
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struct drm_amdgpu_gem_wait_idle_in {
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/** GEM object handle */
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uint32_t handle;
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__u32 handle;
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/** For future use, no flags defined so far */
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uint32_t flags;
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__u32 flags;
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/** Absolute timeout to wait */
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uint64_t timeout;
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__u64 timeout;
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};
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struct drm_amdgpu_gem_wait_idle_out {
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/** BO status: 0 - BO is idle, 1 - BO is busy */
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uint32_t status;
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__u32 status;
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/** Returned current memory domain */
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uint32_t domain;
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__u32 domain;
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};
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union drm_amdgpu_gem_wait_idle {
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@ -284,18 +290,18 @@ union drm_amdgpu_gem_wait_idle {
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struct drm_amdgpu_wait_cs_in {
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/** Command submission handle */
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uint64_t handle;
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__u64 handle;
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/** Absolute timeout to wait */
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uint64_t timeout;
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uint32_t ip_type;
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uint32_t ip_instance;
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uint32_t ring;
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uint32_t ctx_id;
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__u64 timeout;
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__u32 ip_type;
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__u32 ip_instance;
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__u32 ring;
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__u32 ctx_id;
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};
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struct drm_amdgpu_wait_cs_out {
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/** CS status: 0 - CS completed, 1 - CS still busy */
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uint64_t status;
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__u64 status;
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};
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union drm_amdgpu_wait_cs {
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@ -303,17 +309,43 @@ union drm_amdgpu_wait_cs {
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struct drm_amdgpu_wait_cs_out out;
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};
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struct drm_amdgpu_fence {
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__u32 ctx_id;
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__u32 ip_type;
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__u32 ip_instance;
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__u32 ring;
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__u64 seq_no;
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};
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struct drm_amdgpu_wait_fences_in {
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/** This points to uint64_t * which points to fences */
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__u64 fences;
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__u32 fence_count;
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__u32 wait_all;
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__u64 timeout_ns;
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};
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struct drm_amdgpu_wait_fences_out {
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__u32 status;
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__u32 first_signaled;
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};
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union drm_amdgpu_wait_fences {
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struct drm_amdgpu_wait_fences_in in;
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struct drm_amdgpu_wait_fences_out out;
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};
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#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
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#define AMDGPU_GEM_OP_SET_PLACEMENT 1
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/* Sets or returns a value associated with a buffer. */
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struct drm_amdgpu_gem_op {
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/** GEM object handle */
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uint32_t handle;
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__u32 handle;
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/** AMDGPU_GEM_OP_* */
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uint32_t op;
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__u32 op;
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/** Input or return value */
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uint64_t value;
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__u64 value;
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};
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#define AMDGPU_VA_OP_MAP 1
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@ -332,18 +364,18 @@ struct drm_amdgpu_gem_op {
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struct drm_amdgpu_gem_va {
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/** GEM object handle */
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uint32_t handle;
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uint32_t _pad;
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__u32 handle;
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__u32 _pad;
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/** AMDGPU_VA_OP_* */
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uint32_t operation;
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__u32 operation;
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/** AMDGPU_VM_PAGE_* */
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uint32_t flags;
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__u32 flags;
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/** va address to assign . Must be correctly aligned.*/
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uint64_t va_address;
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__u64 va_address;
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/** Specify offset inside of BO to assign. Must be correctly aligned.*/
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uint64_t offset_in_bo;
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__u64 offset_in_bo;
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/** Specify mapping size. Must be correctly aligned. */
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uint64_t map_size;
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__u64 map_size;
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};
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#define AMDGPU_HW_IP_GFX 0
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@ -360,24 +392,24 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
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struct drm_amdgpu_cs_chunk {
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uint32_t chunk_id;
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uint32_t length_dw;
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uint64_t chunk_data;
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__u32 chunk_id;
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__u32 length_dw;
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__u64 chunk_data;
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};
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struct drm_amdgpu_cs_in {
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/** Rendering context id */
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uint32_t ctx_id;
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__u32 ctx_id;
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/** Handle of resource list associated with CS */
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uint32_t bo_list_handle;
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uint32_t num_chunks;
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uint32_t _pad;
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/** this points to uint64_t * which point to cs chunks */
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uint64_t chunks;
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__u32 bo_list_handle;
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__u32 num_chunks;
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__u32 _pad;
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/** this points to __u64 * which point to cs chunks */
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__u64 chunks;
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};
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struct drm_amdgpu_cs_out {
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uint64_t handle;
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__u64 handle;
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};
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union drm_amdgpu_cs {
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@ -394,32 +426,32 @@ union drm_amdgpu_cs {
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#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
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struct drm_amdgpu_cs_chunk_ib {
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uint32_t _pad;
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__u32 _pad;
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/** AMDGPU_IB_FLAG_* */
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uint32_t flags;
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__u32 flags;
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/** Virtual address to begin IB execution */
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uint64_t va_start;
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__u64 va_start;
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/** Size of submission */
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uint32_t ib_bytes;
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__u32 ib_bytes;
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/** HW IP to submit to */
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uint32_t ip_type;
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__u32 ip_type;
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/** HW IP index of the same type to submit to */
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uint32_t ip_instance;
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__u32 ip_instance;
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/** Ring index to submit to */
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uint32_t ring;
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__u32 ring;
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};
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struct drm_amdgpu_cs_chunk_dep {
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uint32_t ip_type;
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uint32_t ip_instance;
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uint32_t ring;
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uint32_t ctx_id;
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uint64_t handle;
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__u32 ip_type;
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__u32 ip_instance;
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__u32 ring;
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__u32 ctx_id;
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__u64 handle;
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};
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struct drm_amdgpu_cs_chunk_fence {
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uint32_t handle;
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uint32_t offset;
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__u32 handle;
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__u32 offset;
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};
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struct drm_amdgpu_cs_chunk_data {
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@ -434,6 +466,7 @@ struct drm_amdgpu_cs_chunk_data {
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*
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*/
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#define AMDGPU_IDS_FLAGS_FUSION 0x1
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#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
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/* indicate if acceleration can be working */
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#define AMDGPU_INFO_ACCEL_WORKING 0x00
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@ -483,6 +516,20 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_DEV_INFO 0x16
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/* visible vram usage */
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#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
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/* number of TTM buffer evictions */
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#define AMDGPU_INFO_NUM_EVICTIONS 0x18
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/* Query memory about VRAM and GTT domains */
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#define AMDGPU_INFO_MEMORY 0x19
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/* Query vce clock table */
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#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
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/* Query vbios related information */
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#define AMDGPU_INFO_VBIOS 0x1B
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/* Subquery id: Query vbios size */
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#define AMDGPU_INFO_VBIOS_SIZE 0x1
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/* Subquery id: Query vbios image */
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#define AMDGPU_INFO_VBIOS_IMAGE 0x2
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/* Query UVD handles */
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#define AMDGPU_INFO_NUM_HANDLES 0x1C
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@ -491,86 +538,119 @@ struct drm_amdgpu_cs_chunk_data {
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struct drm_amdgpu_query_fw {
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/** AMDGPU_INFO_FW_* */
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uint32_t fw_type;
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__u32 fw_type;
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/**
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* Index of the IP if there are more IPs of
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* the same type.
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*/
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uint32_t ip_instance;
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__u32 ip_instance;
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/**
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* Index of the engine. Whether this is used depends
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* on the firmware type. (e.g. MEC, SDMA)
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*/
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uint32_t index;
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uint32_t _pad;
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__u32 index;
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__u32 _pad;
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};
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/* Input structure for the INFO ioctl */
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struct drm_amdgpu_info {
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/* Where the return value will be stored */
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uint64_t return_pointer;
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__u64 return_pointer;
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/* The size of the return value. Just like "size" in "snprintf",
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* it limits how many bytes the kernel can write. */
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uint32_t return_size;
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__u32 return_size;
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/* The query request id. */
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uint32_t query;
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__u32 query;
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union {
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struct {
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uint32_t id;
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uint32_t _pad;
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__u32 id;
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__u32 _pad;
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} mode_crtc;
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struct {
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/** AMDGPU_HW_IP_* */
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uint32_t type;
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__u32 type;
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/**
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* Index of the IP if there are more IPs of the same
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* type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
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*/
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uint32_t ip_instance;
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__u32 ip_instance;
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} query_hw_ip;
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struct {
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uint32_t dword_offset;
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__u32 dword_offset;
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/** number of registers to read */
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uint32_t count;
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uint32_t instance;
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__u32 count;
|
||||
__u32 instance;
|
||||
/** For future use, no flags defined so far */
|
||||
uint32_t flags;
|
||||
__u32 flags;
|
||||
} read_mmr_reg;
|
||||
|
||||
struct drm_amdgpu_query_fw query_fw;
|
||||
|
||||
struct {
|
||||
__u32 type;
|
||||
__u32 offset;
|
||||
} vbios_info;
|
||||
};
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_gds {
|
||||
/** GDS GFX partition size */
|
||||
uint32_t gds_gfx_partition_size;
|
||||
__u32 gds_gfx_partition_size;
|
||||
/** GDS compute partition size */
|
||||
uint32_t compute_partition_size;
|
||||
__u32 compute_partition_size;
|
||||
/** total GDS memory size */
|
||||
uint32_t gds_total_size;
|
||||
__u32 gds_total_size;
|
||||
/** GWS size per GFX partition */
|
||||
uint32_t gws_per_gfx_partition;
|
||||
__u32 gws_per_gfx_partition;
|
||||
/** GSW size per compute partition */
|
||||
uint32_t gws_per_compute_partition;
|
||||
__u32 gws_per_compute_partition;
|
||||
/** OA size per GFX partition */
|
||||
uint32_t oa_per_gfx_partition;
|
||||
__u32 oa_per_gfx_partition;
|
||||
/** OA size per compute partition */
|
||||
uint32_t oa_per_compute_partition;
|
||||
uint32_t _pad;
|
||||
__u32 oa_per_compute_partition;
|
||||
__u32 _pad;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_vram_gtt {
|
||||
uint64_t vram_size;
|
||||
uint64_t vram_cpu_accessible_size;
|
||||
uint64_t gtt_size;
|
||||
__u64 vram_size;
|
||||
__u64 vram_cpu_accessible_size;
|
||||
__u64 gtt_size;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_heap_info {
|
||||
/** max. physical memory */
|
||||
__u64 total_heap_size;
|
||||
|
||||
/** Theoretical max. available memory in the given heap */
|
||||
__u64 usable_heap_size;
|
||||
|
||||
/**
|
||||
* Number of bytes allocated in the heap. This includes all processes
|
||||
* and private allocations in the kernel. It changes when new buffers
|
||||
* are allocated, freed, and moved. It cannot be larger than
|
||||
* heap_size.
|
||||
*/
|
||||
__u64 heap_usage;
|
||||
|
||||
/**
|
||||
* Theoretical possible max. size of buffer which
|
||||
* could be allocated in the given heap
|
||||
*/
|
||||
__u64 max_allocation;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_memory_info {
|
||||
struct drm_amdgpu_heap_info vram;
|
||||
struct drm_amdgpu_heap_info cpu_accessible_vram;
|
||||
struct drm_amdgpu_heap_info gtt;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_firmware {
|
||||
uint32_t ver;
|
||||
uint32_t feature;
|
||||
__u32 ver;
|
||||
__u32 feature;
|
||||
};
|
||||
|
||||
#define AMDGPU_VRAM_TYPE_UNKNOWN 0
|
||||
|
|
@ -584,67 +664,93 @@ struct drm_amdgpu_info_firmware {
|
|||
|
||||
struct drm_amdgpu_info_device {
|
||||
/** PCI Device ID */
|
||||
uint32_t device_id;
|
||||
__u32 device_id;
|
||||
/** Internal chip revision: A0, A1, etc.) */
|
||||
uint32_t chip_rev;
|
||||
uint32_t external_rev;
|
||||
__u32 chip_rev;
|
||||
__u32 external_rev;
|
||||
/** Revision id in PCI Config space */
|
||||
uint32_t pci_rev;
|
||||
uint32_t family;
|
||||
uint32_t num_shader_engines;
|
||||
uint32_t num_shader_arrays_per_engine;
|
||||
__u32 pci_rev;
|
||||
__u32 family;
|
||||
__u32 num_shader_engines;
|
||||
__u32 num_shader_arrays_per_engine;
|
||||
/* in KHz */
|
||||
uint32_t gpu_counter_freq;
|
||||
uint64_t max_engine_clock;
|
||||
uint64_t max_memory_clock;
|
||||
__u32 gpu_counter_freq;
|
||||
__u64 max_engine_clock;
|
||||
__u64 max_memory_clock;
|
||||
/* cu information */
|
||||
uint32_t cu_active_number;
|
||||
uint32_t cu_ao_mask;
|
||||
uint32_t cu_bitmap[4][4];
|
||||
__u32 cu_active_number;
|
||||
__u32 cu_ao_mask;
|
||||
__u32 cu_bitmap[4][4];
|
||||
/** Render backend pipe mask. One render backend is CB+DB. */
|
||||
uint32_t enabled_rb_pipes_mask;
|
||||
uint32_t num_rb_pipes;
|
||||
uint32_t num_hw_gfx_contexts;
|
||||
uint32_t _pad;
|
||||
uint64_t ids_flags;
|
||||
__u32 enabled_rb_pipes_mask;
|
||||
__u32 num_rb_pipes;
|
||||
__u32 num_hw_gfx_contexts;
|
||||
__u32 _pad;
|
||||
__u64 ids_flags;
|
||||
/** Starting virtual address for UMDs. */
|
||||
uint64_t virtual_address_offset;
|
||||
__u64 virtual_address_offset;
|
||||
/** The maximum virtual address */
|
||||
uint64_t virtual_address_max;
|
||||
__u64 virtual_address_max;
|
||||
/** Required alignment of virtual addresses. */
|
||||
uint32_t virtual_address_alignment;
|
||||
__u32 virtual_address_alignment;
|
||||
/** Page table entry - fragment size */
|
||||
uint32_t pte_fragment_size;
|
||||
uint32_t gart_page_size;
|
||||
__u32 pte_fragment_size;
|
||||
__u32 gart_page_size;
|
||||
/** constant engine ram size*/
|
||||
uint32_t ce_ram_size;
|
||||
__u32 ce_ram_size;
|
||||
/** video memory type info*/
|
||||
uint32_t vram_type;
|
||||
__u32 vram_type;
|
||||
/** video memory bit width*/
|
||||
uint32_t vram_bit_width;
|
||||
__u32 vram_bit_width;
|
||||
/* vce harvesting instance */
|
||||
uint32_t vce_harvest_config;
|
||||
__u32 vce_harvest_config;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_hw_ip {
|
||||
/** Version of h/w IP */
|
||||
uint32_t hw_ip_version_major;
|
||||
uint32_t hw_ip_version_minor;
|
||||
__u32 hw_ip_version_major;
|
||||
__u32 hw_ip_version_minor;
|
||||
/** Capabilities */
|
||||
uint64_t capabilities_flags;
|
||||
__u64 capabilities_flags;
|
||||
/** command buffer address start alignment*/
|
||||
uint32_t ib_start_alignment;
|
||||
__u32 ib_start_alignment;
|
||||
/** command buffer size alignment*/
|
||||
uint32_t ib_size_alignment;
|
||||
__u32 ib_size_alignment;
|
||||
/** Bitmask of available rings. Bit 0 means ring 0, etc. */
|
||||
uint32_t available_rings;
|
||||
uint32_t _pad;
|
||||
__u32 available_rings;
|
||||
__u32 _pad;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_num_handles {
|
||||
/** Max handles as supported by firmware for UVD */
|
||||
__u32 uvd_max_handles;
|
||||
/** Handles currently in use for UVD */
|
||||
__u32 uvd_used_handles;
|
||||
};
|
||||
|
||||
#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
|
||||
|
||||
struct drm_amdgpu_info_vce_clock_table_entry {
|
||||
/** System clock */
|
||||
__u32 sclk;
|
||||
/** Memory clock */
|
||||
__u32 mclk;
|
||||
/** VCE clock */
|
||||
__u32 eclk;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_vce_clock_table {
|
||||
struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
|
||||
__u32 num_valid_entries;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/*
|
||||
* Supported GPU families
|
||||
*/
|
||||
#define AMDGPU_FAMILY_UNKNOWN 0
|
||||
#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
|
||||
#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
|
||||
#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
|
||||
#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
|
||||
|
|
|
|||
Loading…
Reference in New Issue